A Dynamically Reconfigurable RF NoC for Many-Core

With the growing number of cores on chips, conventional electrical interconnects reach scalability limits, leading the way for alternatives like Radio Frequency (RF), optical and 3D. Due to the variability of applications, communication needs change over time and across regions of the chip. To address these issues, a dynamically reconfigurable Network on Chip (NoC) is proposed. It uses RF and Orthogonal Frequency Division Multiple Access (OFDMA) to create communication channels whose allocation allows dynamic reconfiguration. We describe the NoC architecture and the distributed mechanism of dynamic allocation. We study the feasibility of the NoC based on state of the art components and analyze its performances. Static analysis shows that, for point to point communications, its latency is comparable with a 256-node electrical mesh and becomes lower for wider networks. A major feature of this architecture is its broadcast capacity. The RF~NoC becomes faster with 32 nodes, achieving a x3 speedup with 1024. Under realistic traffic models, its dynamic reconfigurability provides up to x6 lower latency while ensuring fairness.

[1]  Gokhan Memik,et al.  Tuning Nanophotonic On-Chip Network Designs for Improving Memory Traffic , .

[2]  Vwani P. Roychowdhury,et al.  RF/wireless interconnect for inter- and intra-chip communications , 2001, Proc. IEEE.

[3]  Walter Willinger,et al.  Self-similarity through high-variability: statistical analysis of Ethernet LAN traffic at the source level , 1997, TNET.

[4]  Jason Cong,et al.  Stream arbitration: Towards efficient bandwidth utilization for emerging on-chip interconnects , 2013, TACO.

[5]  Song-Nien Tang,et al.  A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Elad Alon,et al.  A 12.8 GS/s Time-Interleaved ADC With 25 GHz Effective Resolution Bandwidth and 4.6 ENOB , 2014, IEEE Journal of Solid-State Circuits.

[7]  Yuan Xie,et al.  3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC) , 2009, 2009 IEEE International Conference on 3D System Integration.

[8]  Jianyun Hu,et al.  A 25-Gbps 8-ps/mm transmission line based interconnect for on-chip communications in multi-core chips , 2013, 2013 IEEE MTT-S International Microwave Symposium Digest (MTT).

[9]  George Kurian,et al.  ATAC: A 1000-core cache-coherent processor with on-chip optical network , 2010, 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT).

[10]  Qian Xu,et al.  Traffic feature distribution analysis based on exponentially weighted moving average , 2012, 2012 IEEE International Conference on Computer Science and Automation Engineering (CSAE).

[11]  Kai-Wen Yao,et al.  A low-power area-efficient SRAM with enhanced read stability in 0.18-μm CMOS , 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

[12]  Kiyoung Choi,et al.  3D network-on-chip with wireless links through inductive coupling , 2011, 2011 International SoC Design Conference.

[13]  Eby G. Friedman,et al.  3-D Topologies for Networks-on-Chip , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  G FriedmanEby,et al.  3-D topologies for networks-on-chip , 2007 .

[15]  Jung Ho Ahn,et al.  Corona: System Implications of Emerging Nanophotonic Technology , 2008, 2008 International Symposium on Computer Architecture.

[16]  Jason Cong,et al.  CMP network-on-chip overlaid with multi-band RF-interconnect , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[17]  Ian O'Connor,et al.  Optical solutions for system-level interconnect , 2004, SLIP '04.

[18]  C. Nicopoulos,et al.  Design and Management of 3D Chip Multiprocessors Using Network-in-Memory , 2006, ISCA 2006.

[19]  Jongsun Kim,et al.  A Low-Overhead and Low-Power RF Transceiver for Short-Distance On- and Off-Chip Interconnects , 2011, IEICE Trans. Electron..

[20]  John M. Cioffi,et al.  Queue Proportional Scheduling in Gaussian Broadcast Channels , 2006, 2006 IEEE International Conference on Communications.

[21]  Li-Shiuan Peh,et al.  A Statistical Traffic Model for On-Chip Interconnection Networks , 2006, 14th IEEE International Symposium on Modeling, Analysis, and Simulation.

[22]  Radu Marculescu,et al.  Statistical physics approaches for network-on-chip traffic characterization , 2009, CODES+ISSS '09.

[23]  Partha Pratim Pande,et al.  CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless links , 2012, GLSVLSI '12.