Implementation trade-offs in using a restricted data flow architecture in a high performance RISC microprocessor

The implementation of a superscalar, speculative execution SPARC-V9 microprocessor incorporating restricted data flow principles required many design trade-offs. Consideration was given to both performance and cost. Performance is largely a function of cycle time and instructions executed per cycle while cost is primarily a function of die area. Here we describe our restricted data flow implementation and the means with which we arrived at its configuration. Future semi-conductor technology advances will allow these trade-offs to be relaxed and higher performance restricted data flow machines to be built.

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