Automated Verification Pattern Refinement for Virtual Prototypes

Extreme technological and commercial pressures on the design of embedded systems for wireless communications create the need for new design techniques with improved efficiency and higher levels of reuse. Automation of the verification pattern refinement process is one of the most promising candidates for achieving these improvements. An integrated environment for automated verification pattern refinement from the algorithmic to the virtual prototype abstraction level is presented, showing acceleration of the design process, improved reuse, as well as better quality through elimination of manual coding errors.

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