A novel implementation scheme for high area-efficient DCT based on signed stochastic computation

In this paper, we propose a novel implementation scheme of Discrete Cosine Transform (DCT) with ultra high area-efficiency based on signed stochastic computation. Due to the properties of stochastic computation, a new number system, complicated DCT circuits can be realized with very simple logic. According to our analysis, addition operation is the performance and hardware cost bottleneck for stochastic domain. Therefore, our optimization strategies aim at reducing the number of addition operations and designing high precision adder module for signed stochastic computation. A novel high accuracy signed stochastic adder is also provided in this paper. Compared with traditional architecture in Two's Complement System (TCS) domain, the proposed scheme can achieve ultra low hardware cost with less than 10% performance loss. The implementation of stochastic DCT not only meets the performance requirement but also provides low hardware cost and critical path latency.