A 56-ps multi-phase clock time-to-digital convertor based on Artix-7 FPGA

The time-to-digital converter(TDC) is an equipment which aims to measure the accurate time of the edges of the input signal. Our work present an I/O Tile based multi-phase clock time-to-digital TDC, which is implemented in Field-Programmable-Gate-Array(FPGA). A hit signal is sampled by 8 equidistant phase-shifted clocks in the I/O Tile. A differential I/O standard input signal connecting to the I/O Tile is buffered by an input buffer and split into two complementary outputs before feeding to two adjacent ISERDESes. The ISERDESes are configured as the oversample mode, which is used to capture 2 phase DDR data. One ISERDES is driven by 45° and 135° clocks, with the other ISERDES driven by 90° and 180° clocks. Four more clocks are produced by locally inverting logic in the two ISERDESes. An internal PLL is used to generate the clocks. This architecture makes the transmission line more stable and increases the frequency of the sampling clock. To evaluate the TDC's performance, we built a verification system with Xilinx Artix-7 XC7A100T-1 FPGA, which is integrated with 2 TDCs and a readout unit. Tests have been conducted on the performance of the I/O Tile based TDC. Results indicated that the integral nonlinearity is lower than 1 LSB, and the differential nonlinearity is lower than 0.32 LSB. The measurement resolution of 56ps (RMS) is archived.