A Digital LDO With Co-SA Logics and TSPC Dynamic Latches for Fast Transient Response

This letter presents a coarse-fine dual-loop digital low-dropout regulator (DLDO), with combined synchronous and asynchronous logics, designed and measured in a 28-nm bulk CMOS. We adopt a react-then-write two-step logic in the coarse loop for faster transient response. To further shorten the loop latency, we employ true single-phase clock dynamic latches in the coarse loop, and a self-biased continuous-time comparator for voltage droop detection. The proposed DLDO architecture achieves an FoM of 0.59 ps, with a load range of 5–25 mA under a 600-mV supply.

[1]  Mingoo Seok,et al.  20.6 A 0.5V-VIN 1.44mA-class event-driven digital LDO with a fully integrated 100pF output capacitor , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[2]  Ke-Horng Chen,et al.  A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement , 2013, IEEE Journal of Solid-State Circuits.

[3]  Jianping Guo,et al.  A 6-$\mu$ W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology , 2010, IEEE Journal of Solid-State Circuits.

[4]  Philip K. T. Mok,et al.  A Nanosecond-Transient Fine-Grained Digital LDO With Multi-Step Switching Scheme and Asynchronous Adaptive Pipeline Control , 2017, IEEE Journal of Solid-State Circuits.

[5]  Gyu-Hyeong Cho,et al.  A 200-mA Digital Low Drop-Out Regulator With Coarse-Fine Dual Loop in Mobile Application Processor , 2017, IEEE Journal of Solid-State Circuits.

[6]  Yan Lu,et al.  A Dual-Loop Digital LDO Regulator with Asynchronous-Flash Binary Coarse Tuning , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[7]  Mingoo Seok,et al.  A Fully Integrated Digital Low-Dropout Regulator Based on Event-Driven Explicit Time-Coding Architecture , 2017, IEEE Journal of Solid-State Circuits.

[8]  Qiang Li,et al.  A 0.4V 430nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28nm CMOS , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[9]  Patrick P. Mercier,et al.  A Successive Approximation Recursive Digital Low-Dropout Voltage Regulator With PD Compensation and Sub-LSB Duty Control , 2018, IEEE Journal of Solid-State Circuits.

[10]  Mingoo Seok,et al.  A 67.1-ps FOM, 0.5-V-Hybrid Digital LDO With Asynchronous Feedforward Control Via Slope Detection and Synchronous PI With State-Based Hysteresis Clock Switching , 2018, IEEE Solid-State Circuits Letters.

[11]  Kazunori Watanabe,et al.  0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS , 2010, IEEE Custom Integrated Circuits Conference 2010.

[12]  Shi-Jie Wen,et al.  A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[13]  Mingoo Seok,et al.  Comparative study and optimization of synchronous and asynchronous comparators at near-threshold voltages , 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

[14]  Seng-Pan U,et al.  An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator , 2018, IEEE Journal of Solid-State Circuits.

[15]  Christer Svensson,et al.  High-speed CMOS circuit technique , 1989 .

[16]  Arijit Raychowdhury,et al.  All-Digital Low-Dropout Regulator With Adaptive Control and Reduced Dynamic Stability for Digital Load Circuits , 2016, IEEE Transactions on Power Electronics.

[17]  Rui Paulo Martins,et al.  A Fully Integrated Digital LDO With Coarse–Fine-Tuning and Burst-Mode Operation , 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.