Transient Response of a Distributed RLC Interconnect Based on Direct Pole Extraction
暂无分享,去创建一个
[1] Guoqing Chen,et al. An RLC interconnect model based on fourier analysis , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] So-Young Kim,et al. Closed-Form RC and RLC Delay Models Considering Input Rise Time , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.
[3] Roland W. Freund,et al. Efficient linear circuit analysis by Pade´ approximation via the Lanczos process , 1994, EURO-DAC '94.
[4] Gabor C. Temes,et al. Analog MOS integrated circuits , 1988 .
[5] W. Dally,et al. Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[6] Guoqing Chen,et al. Transient simulation of on-chip transmission lines via exact pole extraction , 2008, 2008 IEEE International Symposium on Circuits and Systems.
[7] Kwyro Lee,et al. High-frequency on-chip inductance model , 2002, IEEE Electron Device Letters.
[8] Mattan Kamon,et al. FASTHENRY: a multipole-accelerated 3-D inductance extraction program , 1994 .
[9] Takayasu Sakurai,et al. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs , 1993 .
[10] Hideki Asai,et al. Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects , 2004, Proceedings. 41st Design Automation Conference, 2004..
[11] Yehea I. Ismail,et al. Figures of merit to characterize the importance of on-chip inductance , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[12] Jun Chen,et al. Piecewise linear model for transmission line with capacitive loading and ramp input , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[13] David Thomas,et al. Time-Domain Simulation of Thin Material Boundaries and Thin Panels Using Digital Filters in TLM , 2002 .
[14] Yungseon Eo,et al. A traveling-wave-based waveform approximation technique for thetiming verification of single transmission lines , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[15] James D. Meindl,et al. Compact distributed RLC interconnect models. I. Single line transient, time delay, and overshoot expressions , 2000 .
[16] K. Banerjee,et al. Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).
[17] Lawrence T. Pileggi,et al. AWEsim: Asymptotic Waveform Evaluation for Timing Analysis , 1989, 26th ACM/IEEE Design Automation Conference.
[18] Yu Cao,et al. Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[19] Lawrence T. Pileggi,et al. Performance computation for precharacterized CMOS gates with RC loads , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[20] Jacob K. White,et al. FastCap: a multipole accelerated 3-D capacitance extraction program , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[21] Sharad Mehrotra,et al. Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[22] Yehea I. Ismail,et al. DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[23] R. Saleh. FastCap : A Multipole Accelerated 3-D Capacitance Extraction Program , 1991 .
[24] Jeffrey A. Davis,et al. Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.
[25] Lawrence T. Pileggi,et al. PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.
[26] Andrew B. Kahng,et al. An analytical delay model for RLC interconnects , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[27] Janet Wang,et al. A new multi-ramp driver model with RLC interconnect load , 2004 .
[28] Lawrence T. Pileggi,et al. Modeling the "Effective capacitance" for the RC interconnect of CMOS gates , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[29] David Blaauw,et al. An effective capacitance based driver output model for on-chip RLC interconnects , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[30] Lawrence T. Pileggi,et al. Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[31] Yehea I. Ismail,et al. Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[32] Martin D. F. Wong,et al. Blade and razor: cell and interconnect delay analysis using current-based models , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[33] Mattan Kamon,et al. FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program , 1993, 30th ACM/IEEE Design Automation Conference.
[34] T. Sakurai,et al. Approximation of wiring delay in MOSFET LSI , 1983, IEEE Journal of Solid-State Circuits.
[35] Mattan Kamon,et al. Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures , 1996 .