A low phase noise V‐band 40 NM CMOS phase locked loop for wireless communication

This letter presents a V-band phase-locked loop (PLL) that employs mutual injection-locking voltage controlled oscillator (VCO) and zero blind zone phase frequency detector (PFD) to enhance phase noise performance. This architecture is physically implemented in 40nm CMOS process with a die area of 0.7 mm2. The silicon results demonstrate an in-band phase noise of −90dBc/Hz at 500 kHz offset and −92dBc/Hz at 1MHz offset with 2.5 MHz bandwidth. The PLL draws 40.8 mA current (including output buffer) from a 1.2 V power supply while operating at 60.8 GHz. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:278–283, 2017

[1]  Jri Lee,et al.  A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology , 2008, IEEE Journal of Solid-State Circuits.

[2]  Ziqiang Wang,et al.  A 4.8-mW/Gb/s 9.6-Gb/s 5 $+$ 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  Christer Svensson,et al.  High-speed CMOS circuit technique , 1989 .

[4]  Robert B. Staszewski,et al.  A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS , 2014, IEEE Journal of Solid-State Circuits.

[5]  Tzyy-Sheng Horng,et al.  A Rigorous Analysis of a Phase-Locked Oscillator Under Injection , 2010, IEEE Transactions on Microwave Theory and Techniques.

[6]  A. Bonfanti,et al.  Analysis and design of a 1.8-GHz CMOS LC quadrature VCO , 2002, IEEE J. Solid State Circuits.

[7]  Xiang Yi,et al.  A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology , 2014, IEEE Journal of Solid-State Circuits.

[8]  B. Razavi,et al.  A 60-GHz CMOS receiver front-end , 2006, IEEE Journal of Solid-State Circuits.

[9]  W.A.M. Van Noije,et al.  A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC) , 1999, IEEE J. Solid State Circuits.

[10]  S Sarkar,et al.  A 60 GHz-Standard Compatible Programmable 50 GHz Phase-Locked Loop in 90 nm CMOS , 2010, IEEE Microwave and Wireless Components Letters.

[11]  Piet Wambacq,et al.  A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS , 2015, IEEE Journal of Solid-State Circuits.

[12]  Chulwoo Kim,et al.  A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- $\mu\hbox{m}$ CMOS Process , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[13]  Chung-Yu Wu,et al.  A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-$\mu{\hbox{m}}$ CMOS for $V$ -Band Applications , 2009, IEEE Transactions on Microwave Theory and Techniques.

[14]  Alberto Valdes-Garcia,et al.  A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance , 2015, IEEE Journal of Solid-State Circuits.