Reconfigurable data processing using duplex fault tolerance system

Many digital signal processor designers and manufacturers are facing one big challenge, that is, how to perform complex mathematical function calculations more efficiently. To gain efficiency, it is needed to dig inside our complete designing cycle which contains algorithms, architectures, hardware technology, power supply etc. Fast Fourier Transform (FFT) is widely used transform in digital applications especially in communication systems. An FFT is an important processing block in these systems, which takes most of the hardware complexity in a digital baseband transceiver for instance. Half duplex is one of the redundancy based architecture. The duplex fault tolerance system is used to detect and localization of faulty module which leads to reconfigure the faulty module. Our adapted duplex system is used as a basic structure to increase availability parameters and protect system against single even upsets (SEUs). In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Virtex5 for different types of RTL circuits and fault tolerant architectures. The experimental results demonstrated the effectiveness of the methodology.