Efficient Pairwise Statistical Significance Estimation using FPGAs

In this paper, we present a fast pairwise statistical significance estimator using a Field Programmable Gate Array (FPGA) coprocessor. The running time of the pairwise statistical significance estimation routine is dominated by the hundreds of local alignments it must compute. By offloading the alignment task to an accelerator designed to concurrently process multiple independent alignments, we are able to increase the end-to-end performance of the algorithm by more than 200x over a baseline software implementation. Our proposed accelerator outperforms optimized, multicore software implementations and other FPGA implementations for pairwise statistical significance estimations.

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