A 60-GHz sub-sampling frequency synthesizer using sub-harmonic injection-locked quadrature oscillators

This paper presents a 60-GHz sub-harmonic injection-locked quadrature frequency synthesizer with subsampling operation. This allows the proposed synthesizer to achieve relatively lower in-band phase noise through the use of sub-sampling operation, as well as good out-of-band phase noise through the use of sub-harmonic injection. The proposed synthesizer has been implemented in a standard 65-nm CMOS technology. It can support all 60-GHz channels and achieves a phase noise of -115dBc/Hz at 10MHz offset. The sub-sampling operation helps reducing an integrated jitter from 12ps to 2.1ps. It consumes 20.2mW and 14mW from a 20GHz sub-sampling phase-locked loop (SS-PLL) and a quadrature injection-locked oscillator (QILO), respectively.

[1]  A. Mazzanti,et al.  Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise , 2008, IEEE Journal of Solid-State Circuits.

[2]  Kenichi Okada,et al.  A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers , 2013, IEEE Journal of Solid-State Circuits.

[3]  Win Chaivipas,et al.  A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications , 2011, IEEE Journal of Solid-State Circuits.

[4]  Koichiro Tanaka,et al.  A fully integrated 60GHz CMOS transceiver chipset based on WiGig/IEEE802.11ad with built-in self calibration for mobile applications , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[5]  Robert B. Staszewski,et al.  A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[6]  Koichiro Tanaka,et al.  A Fully Integrated 60-GHz CMOS Transceiver Chipset Based on WiGig/IEEE 802.11ad With Built-In Self Calibration for Mobile Usage , 2013, IEEE Journal of Solid-State Circuits.

[7]  B. Nauta,et al.  A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$ , 2009, IEEE Journal of Solid-State Circuits.

[8]  Shen-Iuan Liu,et al.  A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[9]  Piet Wambacq,et al.  21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[10]  Kenichi Okada,et al.  A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs , 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).

[11]  Xiang Yi,et al.  A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[12]  Kenichi Okada,et al.  Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry , 2013, IEEE Journal of Solid-State Circuits.