Design Techniques for High Performance Intgrated Frequency Synthesizers for Multi-standard Wireless Communication Applications

1 The growing importance of wireless media for voice and data communications is driving a need for higher integration in personal communications transceivers in order to achieve lower cost, smaller form factor, and lower power dissipation. One approach to this problem is to integrate the RF functionality in low-cost CMOS technology together with the baseband transceiver functions. This in turn requires integration of the frequency synthesizer with enough isolation from supply noise to allow the synthesizer to coexist with other on-chip transceiver circuitry and still meet the phase noise performance requirements of the application. This research proposes a differential synthesizer for block-down-convert receivers that achieves improved levels of phase noise and supply rejection performance through the use of fully differential architecture and a wide-bandwidth PLL. Analytical relationships for such a system relating output phase noise to system design parameters and internal noise sources are developed. A prototype systems embodying the design principles, and also embodying new differential circuit configurations which minimize supply coupling is designed, laid out and fabricated. The performance of the prototype synthesizer as a stand alone device is evaluated. The synthesizer is embodied in a complete integrated radio system and the performance of the synthesizer in the complete radio system is also evaluated.

[1]  A. Niknejad,et al.  Analysis , Design , and Optimization of Spiral Inductors and Transformers for Si RF IC ’ s , 1998 .

[2]  M. Steyaert,et al.  An analytical model of planar inductors on lowly doped silicon substrates for high frequency analog design up to 3 GHz , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[3]  Beomsup Kim,et al.  PLL/DLL system noise analysis for low jitter clock synthesizer design , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[4]  Michael H. Perrott,et al.  A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation , 1997, IEEE J. Solid State Circuits.

[5]  Behzad Razavi,et al.  A 3State Phase Detector Can Improve Your Next PLL Design , 1996 .

[6]  Behzad Razavi.  Analysis of Timing Jitter in CMOS Ring Oscilators , 1996 .

[7]  A. Ali,et al.  A 900 MHz frequency synthesizer with integrated LC voltage-controlled oscillator , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[8]  Jacques C. Rudell,et al.  A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications , 1997, IEEE J. Solid State Circuits.

[9]  T. Riley,et al.  Delta-sigma modulation in fractional-N frequency synthesis , 1993 .

[10]  P.R. Gray,et al.  A 1.4 GHz differential low-noise CMOS frequency synthesizer using a wideband PLL architecture , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[11]  J. Rutman.  Characterization of phase and frequency instabilities in precision frequency sources: Fifteen years of progress , 1978, Proceedings of the IEEE.

[12]  M. A. Copeland,et al.  An oversampling delta-sigma frequency discriminator , 1994 .

[13]  Asad A. Abidi,et al.  A 1 GHz CMOS RF front-end IC for a direct-conversion wireless receiver , 1996, IEEE J. Solid State Circuits.

[14]  Behzad Razavi,et al.  A study of phase noise in CMOS oscillators , 1996, IEEE J. Solid State Circuits.

[15]  Michiel Steyaert,et al.  A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler , 1995, IEEE J. Solid State Circuits.

[16]  Li Lin,et al.  A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[17]  J. F. Parker,et al.  A 1.6-GHz CMOS PLL with on-chip loop filter , 1998, IEEE J. Solid State Circuits.

[18]  A. Rofougaran,et al.  A 900 MHz CMOS LC-oscillator with quadrature outputs , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[19]  Ali Hajimiri,et al.  A general theory of phase noise in electrical oscillators , 1998 .

[20]  D. Leeson.  A simple model of feedback oscillator noise spectrum , 1966 .

[21]  강수진.  Charge-Pump Phase-Locked Loops에 관한 연구 및 회로 설계 , 1996 .

[22]  Qiuting Huang,et al.  GSM transceiver front-end circuits in 0.25-/spl mu/m CMOS , 1999 .

[23]  Thomas H. Lee,et al.  The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES , 2003 .

[24]  Behzad Razavi.  A Digital Phase and Frequency Sensitive Detector , 1996 .

[25]  Michiel Steyaert,et al.  Low-noise voltage-controlled oscillators using enhanced LC-tanks , 1995 .

[26]  Ali M. Niknejad,et al.  Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs , 1998, IEEE J. Solid State Circuits.

[27]  J. I. Brown,et al.  A digital phase and frequency-sensitive detector , 1971 .

[28]  Jacques C. Rudell,et al.  An Integrated GSM/DECT Receiver: Design Specifications , 1998 .

[29]  Asad A. Abidi,et al.  A 1 GHz CMOS RF front-end IC for a direct-conversion wireless receiver , 1998 .

[30]  R.G. Meyer,et al.  Phase noise in LC oscillators , 2000, IEEE Journal of Solid-State Circuits.

[31]  Behzad Razavi.  Analysis, modeling, and simulation of phase noise in monolithic voltage-controlled oscillators , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[32]  J.N. Burghartz,et al.  A 3 V 4 GHz nMOS voltage-controlled oscillator with integrated resonator , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[33]  Beomsup Kim,et al.  Analysis of timing jitter in CMOS ring oscillators , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[34]  J. H. Havens,et al.  A 2.7 V to 4.5 V single-chip GSM transceiver RF integrated circuit , 1995 .

[35]  Andrew Z Grzegorek,et al.  ∝s Settling and 2Mb/s Closed Loop Modulation , 2000 .

[36]  G. Chien,et al.  A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications , 2000, IEEE Journal of Solid-State Circuits.

[37]  A. Abidi,et al.  Noise in relaxation oscillators , 1983 .

[38]  Chuan Yi Tang,et al.  A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..

[39]  J. Lundberg,et al.  An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors(Special Issue on the 1994 VLSI Circuits Symposium) , 1995 .