One of the most serious problems in a highly multiple parallel processing system involves memory access contention. In the hierarchically structured access mechanism, the number of simultaneous access paths increases with degree of parallelism. Consequently, it is considered as a configuration suited to a highly multiple parallel system. This paper uses a queue model to analyze the hierarchical routing bus (H-R bus), which is an access mechanism with a hierarchical structure. The paper further makes a quantitative evaluation of the locality in data access. Based on the derived theoretical expressions and measured results obtained by executing several test programs on the H-R bus-connected parallel computer, the H-R bus performance is evaluated. The results obtained in this paper are as follows: (1) Low external data access rates (i.e., external data access time/processing time) indicate that the H-R bus-connected multiprocessor system operates with high efficiency even under high multiplicity. (2) Under sufficient access locality, even high external data access rates do not unduly impair efficiency. Although the above properties have qualitatively been known before, this paper derives theoretical expressions for the properties, supported by experiments.
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