A high-performance OC-12/OC-48 queue design prototype for input-buffered ATM switches

This paper presents the design and prototype of an intelligent, 3-dimensional-queue (3DQ) for high-performance, scalable, input-buffered ATM switches. The 3DQ uses pointers and linked lists to organize ATM cells into multiple virtual queues according to priority, destination, and virtual connection. It enforces per-virtual connection quality-of-service (QoS) and eliminates head-of-line (HOL) blocking. Using field-programmable-gate-array (FPGA) devices, our prototype hardware can process ATM cells at 622 Mb/s (OC-12). Using more aggressive technology (multi-chip-module (MCM) and fast GaAs logic), the same 3DQ can process cells at 2.5 Gb/s (OC-48). Using the 3DQ and matrix-unit-cell-scheduler (MUCS) as essential components, an input-buffered ATM switch system has been designed, which can achieve near-100% link bandwidth utilization.

[1]  Samuel P. Morgan,et al.  Input Versus Output Queueing on a Space-Division Packet Switch , 1987, IEEE Trans. Commun..

[2]  G. Goldszmidt,et al.  ShockAbsorber: a TCP connection router , 1997, GLOBECOM 97. IEEE Global Telecommunications Conference. Conference Record.

[3]  Robert C. Frye,et al.  An I/O CMOS buffer set for silicon multichip module's (MCM) , 1993, Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93.

[4]  Kai Y. Eng,et al.  A growable packet (ATM) switch architecture: design principles and application , 1992, IEEE Trans. Commun..

[5]  S. C. Liew Performance of input-buffered and output-buffered ATM switches under bursty traffic: simulation study , 1990, [Proceedings] GLOBECOM '90: IEEE Global Telecommunications Conference and Exhibition.

[6]  Ahmed K. Elhakeem,et al.  Traffic analysis of a local area network with a star topology , 1988, IEEE Trans. Commun..

[7]  Y. Hamazumi,et al.  Parallel contention resolution control for input queueing ATM switches , 1992 .

[8]  Nick McKeown,et al.  A Starvation-free Algorithm For Achieving 100% Throughput in an Input- Queued Switch , 1999 .

[9]  John W. Lockwood,et al.  FPGA prototype queuing module for high performance ATM switching , 1994, Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit.

[10]  Thomas Kailath,et al.  A broadband packet switch architecture with input and output queueing , 1994, 1994 IEEE GLOBECOM. Communications: The Global Bridge.

[11]  Anthony S. Acampora,et al.  The Knockout Switch: A Simple, Modular Architecture for High-Performance Packet Switching , 1987, IEEE J. Sel. Areas Commun..

[12]  Thomas E. Anderson,et al.  High speed switch scheduling for local area networks , 1992, ASPLOS V.

[13]  A. Pattavina,et al.  Nonblocking architectures for ATM switching , 1993, IEEE Communications Magazine.

[14]  John W. Lockwood,et al.  Efficient input queuing and cell scheduling scheme for scalable ultrabroadband optoelectronic ATM switching , 1995, Other Conferences.

[15]  Pravin Varaiya,et al.  Scheduling cells in an input-queued switch , 1993 .

[16]  Alexander G. Fraser,et al.  Xunet 2: a nationwide testbed in high-speed networking , 1992, [Proceedings] IEEE INFOCOM '92: The Conference on Computer Communications.

[17]  Kai Y. Eng,et al.  Improving the performance of input-queued ATM packet switches , 1992, [Proceedings] IEEE INFOCOM '92: The Conference on Computer Communications.

[18]  A. Jajszczyk,et al.  ATM shared-memory switching architectures , 1994, IEEE Network.

[19]  T. J. Gabara,et al.  Performance evaluation of MCM chip-to-chip interconnections using custom I/O buffer designs , 1993, Sixth Annual IEEE International ASIC Conference and Exhibit.

[20]  H. Jonathan Chao,et al.  Abacus switch: a new scalable multicast ATM switch , 1995, Other Conferences.

[21]  Sung-Mo Kang,et al.  Scalable optoelectronic ATM networks: the iPOINT fully functional testbed , 1995 .

[22]  Kazuyoshi Oshima,et al.  622 Mb/s 8/spl times/8 shared multibuffer ATM switch with hierarchical queueing and multicast functions , 1993, Proceedings of GLOBECOM '93. IEEE Global Telecommunications Conference.

[23]  Gene W. Shen,et al.  SPARC64: a 64-b 64-active-instruction out-of-order-execution MCM processor , 1995 .

[24]  J. Chun,et al.  0.5 /spl mu/m AlGaAs/GaAs HMESFET technology for digital VLSI products , 1993, 15th Annual GaAs IC Symposium.

[25]  Kai Y. Eng,et al.  A 160-Gb/s ATM switch prototype using the concentrator-based growable switch architecture , 1995, Proceedings IEEE International Conference on Communications ICC '95.

[26]  Hitoshi Uematsu,et al.  A 1.5 Gb/s 8 X 8 Cross-Connect Switch Using a Time Reservation Algorithm , 1991, IEEE J. Sel. Areas Commun..

[27]  R. Goyal Designing a 100 MHz SPARC dual processor using MCM-L packaging technology and microwave design techniques , 1994, 1994 IEEE MTT-S International Microwave Symposium Digest (Cat. No.94CH3389-4).