Smart Stacking™ and Smart Cut™ technologies for wafer level 3D integration

The wafer stacking technology for 3D integration requires high quality bonding interfaces with uniform bonding films. Two wafer level stacking technologies - Smart Stacking™ and Smart Cut™ - are developed to address the manufacturing challenges for improved process cost efficiency.

[1]  Didier Landru,et al.  Low temperature direct wafer to wafer bonding for 3D integration: Direct bonding, surface preparation, wafer-to-wafer alignment , 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

[2]  Pierric Gueguen,et al.  Full characterization of Cu/Cu direct bonding for 3D integration , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[3]  J. Dechamp,et al.  Recent developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking , 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

[4]  L. Di Cioccio,et al.  Investigation of stress induced voiding and electromigration phenomena on direct copper bonding interconnects for 3D integration , 2011, 2011 International Electron Devices Meeting.

[5]  Qiang Xu,et al.  Yield enhancement for 3D-stacked memory by redundancy sharing across dies , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[6]  S. Ramanathan,et al.  Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology , 2006, IEEE Electron Device Letters.

[7]  M. Bruel Silicon on insulator material technology , 1995 .

[8]  L. Clavelier,et al.  Copper direct bonding: An innovative 3D interconnect , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[9]  Thomas Signamarcheix,et al.  Wafer Level 3D Stacking Using Smart Cut and Metal-Metal Direct Bonding Technology , 2013 .

[10]  T. Matthias,et al.  Recent advances in submicron alignment 300 mm copper-copper thermocompressive face-to-face wafer-to-wafer bonding and integrated infrared, high-speed FIB metrology , 2010, 2010 IEEE International Interconnect Technology Conference.

[11]  Suss Micro Wafer and Die Bonding Technologies for 3D Integration , 2010 .

[12]  I. Cayrefourcq,et al.  Systematic study of the splitting kinetic of H/He co-implanted substrate , 2003, 2003 IEEE International Conference on SOI.

[13]  Mariam Sadaka,et al.  Building blocks for wafer-level 3D integration , 2009 .