论文信息 - Hot spot dynamics in quasivertical DMOS under ESD stress

Hot spot dynamics in quasivertical DMOS under ESD stress

Quasivertical DMOS transistors in a 90V Smart Power Technology are studied under ElectroStatic Discharge (ESD) stress. Movement of current filaments and multiple hot spots are observed under snap-back conditions. The hot spot dynamics are explained in terms of the movement of a base push-out region across the cell field as a consequence of the temperature dependence of avalanche generation. The described mechanisms help homogenizing the time averaged current density distribution and enhance the device robustness against ESD events.

[1] P. L. Hower,et al. Avalanche injection and second breakdown in transistors , 1970 .

[2] V. Dubec,et al. Single-shot thermal energy mapping of semiconductor devices with the nanosecond resolution using holographic interferometry , 2002, IEEE Electron Device Letters.

[3] Andreas Daniel Stricker. Technology computer aided design of ESD protection devices , 2001 .

[4] C. T. Kirk,et al. A theory of transistor cutoff frequency (fT) falloff at high current densities , 1962, IRE Transactions on Electron Devices.

[5] V. Parthasarathy,et al. A double RESURF LDMOS with drain profile engineering for improved ESD robustness , 2002, IEEE Electron Device Letters.