New TSPC latches and flipflops minimizing delay and power
暂无分享，去创建一个
In the new TSPC flipflops, speed and power bottlenecks of the original TSPC and the existing differential flipflops are removed. Delays are reduced by factors of 2.0, 2.2 and 2.4 for the dynamic, the semi-static and the fully-static flipflops, respectively. In the same time, power consumptions are also reduced so the power-delay products are reduced by factors of 3.5, 3.4 and 6.5 for A=0.25. Moreover, the clock loads are minimized, the circuits are completely non-precharged and the logic-related transistors are purely n-type in both n-latches and p-latches. It means that all logic operations can be done completely by n-transistors, which gives a very large speed advantage to this kind of CMOS circuits.
[1] Christer Svensson,et al. High-speed CMOS circuit technique , 1989 .
[2] Christer Svensson,et al. A true single-phase-clock dynamic CMOS circuit technique , 1987 .
[3] Chung-Yu Wu,et al. Low-voltage low-power CMOS true-single-phase clocking scheme with locally asynchronous logic circuits , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.