Systolic Processors as Second Level Triggers for High Energy Physics Experiments

This paper describes two fully programmable systolic processors for second level trigger processing in high energy physics experiments at CERN, Geneva, Switzerland. One of them has been used successfully since spring 1991 at the CERES/NA45 experiment for the recognition of Cherenkov rings in a ring image Cherenkov (RICH) detector. The processor consists of a 1m 2 systolic array of 176160, i.e. over 28,000 processing elements which are packed into 2220 VLSI chips that have been designed in 2 CMOS standard cell technology. The second processor, the ENABLE machine, is under design within the EAST/RD{11 collaboration at CERN that studies the data processing problems foreseen for the next generation of colliders like LHC, SSC, etc. It has been designed for the TRD detector of the LHC as a test application where a complex trigger decision has to be taken in less than 10 s. The ENABLE machine identiies arbitrary patterns in binary images by direct template matching. For each pattern the coincidences of the mask template and the picture under study are histogrammed. The machine is scalable in picture size as well as in the number of patterns processed concurrently. It exploits programmable gate array technology so that its architecture can be programmed into standard hardware. Both architectures and the consequences of their diierent implementation are discussed.