Visualizing effect of dependency in superscalar pipelining

Pipelining is a particularly effective way of getting parallelism in easiest manner. It is an implementation technique, where multiple jobs are performed in overlapped manner. Superscalar pipeline is the type of pipeline which can issue more than one instruction in one clock cycle. But dependency is the major problem for any type of pipeline. In this paper we describe the visualization system for analyzing the effect of dependency in superscalar processor. To visualize, a simulator is developed in C language. In the simulator CPI, IPC, clock cycle wise stage occupation is shown in detail and subsequently it also calculates total number of clock cycles, total pipeline stalls.