Power-efficient implementation of turbo decoder in SDR system

Turbo coding is widely used in wireless communication. Efficient implementation of turbo codes has significant impact on the power efficiency of mobile systems. Especially, as the need for software defined radio (SDR) system is growing, the appropriate selection of DSP processors becomes an important design issue. In this work, we show that using a processor that operates using the logarithmic number system is more power efficient for executing the turbo codes than traditional fixed point and floating point processors. Further, we modify the Logarithmic Number System (LNS) processor to support less accurate addition to reduce power consumed by max*, an important operation performed during turbo decoding. Our simulation shows that this optimization reduces the power consumption of turbo coding by 27.6% with negligible impact on the signal to noise ratio.

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