An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters

An area-effcient systolic architecture for realtime, programmable-coefficient finite impulse response (FIR) filters is presented. A technique called pipelined clustering is introduced to derive the architecture in which a number of filter tap computations are multiplexed in an appropriately pipelined processor. This multiplezing is made possible by the fact that the processor is clocked at the highest possible frequency under the given. technology and design constraints. Reduction in hardware proportional to the ratio of data arrival period and clock period is achieved. The proposed systolic architecture is 100% efficient and has the same throughput and latency and approximately the same power dissipation as an unclustered array. The architecture is completely specified, including a description, of the multip1exers and synchronisation delays that are required.