Multiprocessor mapping of process networks: a JPEG decoding case study

We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a structured approach for implementing process networks. We use process networks as re-usable and architecture-independent functional specifications. The method facilitates the cost-driven and constraint-driven source code transformation of process networks into architecture-specific implementations in the form of communicating tasks. We apply the method to implement a JPEG decoding process network in software on a set of MIPS processors. We apply three transformations to optimize synchronization rates and data transfers and to exploit data parallelism for this target architecture. We evaluate the impact of the source code transformations and the performance of the resulting implementations in terms of design time, execution time, and code size. The results show that process networks can be implemented quickly and efficiently on embedded multiprocessor systems.

[1]  Evert-Jan D. Pol,et al.  Design of multi-tasking coprocessor control for Eclipse , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

[2]  Nikil D. Dutt,et al.  Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors , 2001, IEEE Des. Test Comput..

[3]  Erwin A. de Kock,et al.  COSY communication IP's , 2000, Proceedings 37th Design Automation Conference.

[4]  Luciano Lavagno,et al.  Synthesis of embedded software using free-choice Petri nets , 1999, DAC '99.

[5]  Erwin A. de Kock,et al.  YAPI: application modeling for signal processing systems , 2000, Proceedings 37th Design Automation Conference.

[6]  Gregory K. Wallace,et al.  The JPEG still picture compression standard , 1992 .

[7]  Alberto L. Sangiovanni-Vincentelli,et al.  System-level design: orthogonalization of concerns andplatform-based design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Rudy Lauwereins,et al.  Task concurrency management experiment for power-efficient speed-up of embedded MPEG4 IM1 player , 2000, Proceedings 2000. International Workshop on Parallel Processing.

[9]  Gilles Kahn,et al.  The Semantics of a Simple Language for Parallel Programming , 1974, IFIP Congress.

[10]  Twan Basten,et al.  Efficient Execution of Process Networks , 2001 .

[11]  Luca Benini,et al.  Source code transformation based on software cost analysis , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

[12]  Luciano Lavagno,et al.  Task generation and compile-time scheduling for mixed data-control embedded software , 2000, Proceedings 37th Design Automation Conference.

[13]  P. Stravers,et al.  Homogeneous multiprocessing and the future of silicon design paradigms , 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

[14]  Erik Brockmeyer,et al.  Data and memory optimization techniques for embedded systems , 2001, TODE.

[15]  Om Prakash Gangwal,et al.  A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).