Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers

This brief proposes lower power lower delay design for CMOS tapered buffers. A slight increase in the threshold voltage is shown to have an exponential effect in reducing the total power dissipation. The corresponding increase in the propagation delay is compensated for by increasing the number of buffer stages such that there is still an overall significant reduction in the total power dissipation. As compared to the constant threshold voltage design based on a cost function of PT2, the proposed scheme can lead to either a power dissipation reduction of about 70% while maintaining the same delay, or up to 30% in power dissipation with 10% propagation delay reduction, respectively, in 65-nm technology with VDD = 1 V, minimum size gate capacitance, Cg = 1.5 fF, and minimum size output capacitance, Co = 1 fF. Closed-form expressions that give the optimum threshold voltage and number of stages are presented.

[1]  L.W. Linholm,et al.  An optimized output stage for MOS integrated circuits , 1975, IEEE Journal of Solid-State Circuits.

[2]  Richard C. Jaeger,et al.  Comments on "An optimized output stage for MOS integrated circuits" [with reply] , 1975 .

[3]  Hendrikus J. M. Veendrick,et al.  Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .

[4]  F. S. Lai.  A generalized algorithm for CMOS circuit delay, power, and area optimization , 1988 .

[5]  A. Tuszynski,et al.  CMOS tapered buffer , 1990 .

[6]  M. Bohr.  Interconnect scaling-the real limiter to high performance ULSI , 1995, Proceedings of International Electron Devices Meeting.

[7]  Eby G. Friedman,et al.  A unified design methodology for CMOS tapered buffers , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[8]  M. Kinugawa,et al.  Design Methodology of Deep Submicron CMOS Devices for 1 V Operation (Special Issue on Low-Power LSI Technologies) , 1996 .

[9]  W. Dally.  Interconnect-limited VLSI architecture , 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

[10]  James D. Meindl,et al.  A physical alpha-power law MOSFET model , 1999 .

[11]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[12]  R. Montoye,et al.  Beyond Moore's Law: the interconnect era , 2004, Computing in Science & Engineering.

[13]  Ching-Li Lee,et al.  Low-Power Small-Area Digital I/O Cell , 2005, IEEE Trans. Circuits Syst. II Express Briefs.

[14]  Haibo He,et al.  A Novel Low-Power Logic Circuit Design Scheme , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.