Algorithms for transient three-dimensional mixed-level circuit and device simulation

Algorithms for transient mixed-level circuit and device simulation using a full two-carrier three-dimensional (3-D) device simulator SIERRA and the circuit simulator SPICE3 are presented. Circuit and device simulator coupling algorithms that are suited for two-dimensional mixed-level circuit and device simulation using direct solvers cannot be successfully employed when iterative solution techniques are used in 3-D device simulation. New algorithms to couple the circuit and 3-D device simulator have been developed and evaluated. The importance of 3-D mixed-level circuit and device simulation is demonstrated by applying it to single-event upset in CMOS SRAM cells. >

[1]  Siegfried Selberherr,et al.  Connection of Network and Device Simulation , 1990, Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits.

[2]  H.T. Weaver,et al.  Memory SEU simulations using 2-D transport calculations , 1985, IEEE Electron Device Letters.

[3]  Ping Yang,et al.  SIERRA: a 3-D device simulator for reliability modeling , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Kartikeya Mayaram,et al.  A parallel block-diagonal preconditioned conjugate-gradient solution algorithm for circuit and device simulations , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[5]  Gernot Heiser,et al.  Three-dimensional numerical semiconductor device simulation: algorithms, architectures, results , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Kartikeya Mayaram,et al.  A Concurrent Conjugate-gradient-based 3-d Device Equation Solver Including Latency , 1990, Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits.

[7]  Rainer Laur,et al.  MEDUSA--A Simulator for Modular Circuits , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  J. S. Browning,et al.  An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM , 1987, IEEE Transactions on Nuclear Science.

[9]  Kartikeya Mayaram,et al.  Coupling algorithms for mixed-level circuit and device simulation , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  P. Sonneveld CGS, A Fast Lanczos-Type Solver for Nonsymmetric Linear systems , 1989 .

[11]  M. S. Mock,et al.  Analysis of mathematical models of semiconductors devices , 1983 .

[12]  John Choma,et al.  Mixed-mode PISCES-SPICE coupled circuit and device solver , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  R. A. Rohrer Circuit partitioning simplified , 1988 .

[14]  A. Ochoa,et al.  A proposed new structure for SEU immunity in SRAM employing drain resistance , 1987, IEEE Electron Device Letters.

[15]  Chang Huang,et al.  A two-dimensional integrated device/circuit numerical model for GaAs DCFL gate simulation , 1990 .

[16]  Thomas L. Quarles THE SPICE3 IMPLEMENTATION GUIDE , 1989 .

[17]  T. Kobori Device Simulation Intending Small Scale Circuit Level Analysis , 1990, Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits.

[18]  Savvas G. Chamberlain,et al.  CHORD: a modular semiconductor device simulation development tool incorporating external network models , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..