Job arrival rate aware scheduling for asymmetric multi-core servers in the dark silicon era

The rate at which jobs arrive for processing at servers in a data-center (i.e., the job arrival rate) can vary significantly with time. Each server in a data-center is a multi-core processor, allowing jobs to be processed with different degrees of parallelism (DoPs) (i.e., number of threads per job). In this paper, we show both analytically and empirically that the optimal DoP that minimizes mean service time varies with job arrival rate. In addition, we show that for asymmetric multi-core server processors (i.e., processors with multiple clusters, each consisting of cores of a different type, and assuming that only one cluster is active at any given time while the others are dark), the best cluster to select is also dependent on job arrival rate. Based on these observations, we propose a run-time scheduler that determines the optimal DoP and performs inter-cluster migration to minimize mean service time within a power budget. Experimental results demonstrate significant reduction in mean service time compared to job arrival rate unaware schedulers.

[1]  Jian Li,et al.  Dynamic power-performance adaptation of parallel computation on chip multiprocessors , 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..

[2]  Mahmut T. Kandemir,et al.  Steep-Slope Devices: From Dark to Dim Silicon , 2013, IEEE Micro.

[3]  Hiroshi Nakamura,et al.  Scalability-based manycore partitioning , 2012, 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT).

[4]  Junjie Wu,et al.  BigHouse: A simulation infrastructure for data center systems , 2012, 2012 IEEE International Symposium on Performance Analysis of Systems & Software.

[5]  Brian Jeff Advances in big.LITTLE Technology for Power and Energy Savings Improving Energy Efficiency in High-Performance Mobile Platforms , 2012 .

[6]  Muhammad Shafique,et al.  darkNoC: Designing energy-efficient network-on-chip with multi-Vt cells for dark silicon , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[7]  Steven Swanson,et al.  QSCORES: Trading dark silicon for scalable energy efficiency with quasi-specific cores , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[8]  Erhard Rahm Dynamic Load Balancing in Parallel Database Systems , 1996, Euro-Par, Vol. I.

[9]  Siddharth Garg,et al.  Cherry-picking: Exploiting process variations in dark-silicon homogeneous chip multi-processors , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[10]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[11]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[12]  O Seongil,et al.  McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling , 2013, 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

[13]  Arun Raman,et al.  Parallelism orchestration using DoPE: the degree of parallelism executive , 2011, PLDI '11.

[14]  Siddharth Garg,et al.  HaDeS: Architectural synthesis for heterogeneous dark silicon chip multi-processors , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[15]  Christian Bienia,et al.  PARSEC 2.0: A New Benchmark Suite for Chip-Multiprocessors , 2009 .

[16]  Jason M. Allred,et al.  Designing for dark silicon: a methodological perspective on energy efficient systems , 2012, ISLPED '12.

[17]  Muhammad Shafique,et al.  ASER: Adaptive soft error resilience for Reliability-Heterogeneous Processors in the dark silicon era , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[18]  Heba Khdr,et al.  TSP: Thermal Safe Power - Efficient power budgeting for many-core systems in dark silicon , 2014, 2014 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[19]  Antony I. T. Rowstron,et al.  Bridging the tenant-provider gap in cloud services , 2012, SoCC '12.

[20]  Norman P. Jouppi,et al.  Single-ISA heterogeneous multi-core architectures for multithreaded workload performance , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[21]  Marios C. Papaefthymiou,et al.  Computational sprinting , 2012, IEEE International Symposium on High-Performance Comp Architecture.

[22]  Luiz André Barroso,et al.  The Case for Energy-Proportional Computing , 2007, Computer.

[23]  Muhammad Shafique,et al.  The EDA challenges in the dark silicon era , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[24]  Lieven Eeckhout,et al.  Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation , 2011, 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC).

[25]  Karthikeyan Sankaralingam,et al.  Dark Silicon and the End of Multicore Scaling , 2012, IEEE Micro.

[26]  Christoforos E. Kozyrakis,et al.  Evaluating MapReduce for Multi-core and Multiprocessor Systems , 2007, 2007 IEEE 13th International Symposium on High Performance Computer Architecture.

[27]  Vanchinathan Venkataramani,et al.  Hierarchical power management for asymmetric multi-core in dark silicon era , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[28]  Peng Qi,et al.  The Evolution of Wikipedia , 2013 .

[29]  Muhammad Shafique,et al.  Self-adaptive hybrid Dynamic Power Management for many-core systems , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[30]  Michael Bedford Taylor,et al.  Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse , 2012, DAC Design Automation Conference 2012.

[31]  Ki-Seok Chung,et al.  Benefits of the big . LITTLE Architecture , 2012 .