A switching noise vision of the optimization techniques for low-power synthesis

Different techniques used by a CAD tool that automatically optimize power consumption at gate-level circuit have been investigated in terms of switching noise generation. Such techniques, clock-gating, sleep-mode and others at a gate-level are usual saving power techniques, but are rarely applied to switching noise reduction. The reduction of peaks in supply current is of great interest due to their impact in sensitive parts of a circuit. An estimation of these peaks has been done at a gate level by two different tools (PrimePower and NanoSim, both from Synopsys) providing both the power supply current waveform along time, the average and the peak power for different synthesized circuits to check the effectiveness of such low-power techniques for switching noise reduction. As conclusions, although both tools provide an estimation of peak power, only NanoSim gives accurate values, and how these optimization techniques for low-power are, in general, useful for switching noise reduction.

[1]  M. Vesterbacka,et al.  A strategy for reducing clock noise in mixed-signal circuits , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[2]  Kevin J. Nowka,et al.  Power gating with multiple sleep modes , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[3]  Pilar Parra,et al.  Reduction of Switching Noise in Digital CMOS Circuits by Pin Swapping of Library Cells 1 , 2001 .

[4]  Hugo De Man,et al.  Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Manoj Sachdev,et al.  An overview of substrate noise reduction techniques , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

[6]  Ian O'Connor,et al.  Extremely Low-Power Logic , 2004, DATE '04.

[7]  Xavier Aragones,et al.  Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs , 1999 .

[8]  Antonio J. Acosta,et al.  Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits , 2005, SPIE Microtechnologies.

[9]  Gabriella Trucco,et al.  Effects of digital switching noise on analog voltage references in mixed-signal CMOS ICs , 2006, SBCCI '06.

[10]  Antonio Rubio,et al.  An investigation on the relation between digital circuitry characteristics and power supply noise spectrum in mixed-signal CMOS integrated circuits , 2005, Microelectron. J..

[11]  Kaushik Roy,et al.  Low Power Synthesis of Dynamic Logic Circuits Using Fine-Grained Clock Gating , 2006, Proceedings of the Design Automation & Test in Europe Conference.