A 3.5–6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise
暂无分享,去创建一个
Yue Chen | Robert B. Staszewski | Ping Lu | Ying Wu | Mina Shahmohammadi | R. Staszewski | Ying Wu | Yue Chen | P. Lu | M. Shahmohammadi
[1] Ahmed Elkholy,et al. A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC , 2015, IEEE Journal of Solid-State Circuits.
[2] Ehsan Afshari,et al. A Low-Phase-Noise Wide-Tuning-Range Oscillator Based on Resonant Mode Switching , 2012, IEEE Journal of Solid-State Circuits.
[3] Giovanni Marzin,et al. A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power , 2011, 2011 IEEE International Solid-State Circuits Conference.
[4] Kathleen Philips,et al. 9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
[5] K. Muhammad,et al. All-digital PLL and transmitter for mobile phones , 2005, IEEE Journal of Solid-State Circuits.
[6] Robert Bogdan Staszewski,et al. A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-ΔΣ time-to-digital converter for ADPLL , 2015, 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).