Challenge of MTJ/MOS-hybrid logic-in-memory architecture for nonvolatile VLSI processor

A new logic-circuit style based on nonvolatile logic-in-memory architecture is proposed for realizing compact, low-power logic and highly reliable VLSI processors with parallel data accessibility. Since nonvolatile storage elements such as magnetic tunnel junction (MTJ) devices are distributed over a logic-circuit plane in the proposed style, wide memory bandwidth as well as instant power gating without escaping/reloading data can be realized. As typical examples, and an MTJ-based nonvolatile Ternary Content-Addressable Memory, an MTJ-based nonvolatile look-up table circuit for an instant power-ON/OFF field programmable gate array and a post-process variation-resilient logic-circuit design using MTJ devices are implemented and their superior performances are demonstrated in comparison with a corresponding CMOS-only-based realization.