Design of a tunable CML-based differential ring oscillator with short start-up and switching transiets

In this work, an improved Current-Mode-Logic-based (CML) ring oscillator is designed for use in an on-chip Vernier-based Time-to-Digital Converter (TDC) that could be used to measure timing specifications of high-speed signals, such as period and jitter, in the picoseconds range. The oscillator is designed with two tuning mechanisms to achieve coarse and fine tuning resolutions. The period of the oscillator can either be tuned from 0.5% to 10% or from 0.05% to 2.5% of the oscillator zero-resolution period (550 MHz) during coarse and fine resolutions of operation, respectively. A detailed study and characterization of the impact of the oscillator period variations when it is switched ON (start-up transient) and when the oscillator period is switched from one resolution to another (switching transient) on a Vernier oscillator-based TDC time interval is presented. The impact of oscillator period deviations in steady state and externally introduced random noise on the TDC performance is also shown analytically. A metric to characterize the effects of these transients and jitter on the time interval measurement is derived to benchmark the performance of the ring oscillator. This metric can be used to evaluate performance of any oscillators for its stability. Simulation results from the optimized ring oscillator show that the effects of the start-up transient become negligible after four clock cycles and that of the effects of switching transient become negligible instantaneously. Simulation also shows that the oscillator can achieve a stable steady state period, down to less than 0.5fs, which is the simulator precision. In reality, the oscillator will contain some random jitter due to external noise. This kind of jitter can be eliminated through averaging.

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