8 Gb MLC (multi-level cell) NAND flash memory using 63 nm process technology

For the first time, 8 Gb multi-level cell (MLC) NAND flash memory with 63 nm design rule is developed for mass storage applications. Its unit cell size is 0.0164 /spl mu/m/sup 2/, the smallest ever reported. ArF lithography with off-axis illumination (OAI) was employed for critical layers. In addition, self-aligned floating poly-silicon gate (SAP), tungsten gate with an optimized re-oxidation process, oxide spacer and tungsten bit-line (BL) with low resistance were implemented.

[1]  S.N. Keeney.  A 130 nm generation high density Etox/sup TM/ flash memory technology , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[2]  Jae-Duk Lee,et al.  Effects of floating-gate interference on NAND flash memory cell operation , 2002, IEEE Electron Device Letters.