A unified architecture for speed-binning and circuit failure prediction and detection

With the continual scaling of semiconductor process technology, the circuit timing is increasingly impacted by process variations. It is thus important to categorize high-speed digital circuits into multiple bins of different performances. However, the speed-binning process typically needs very long test application time. In this paper, we proposed a unified architecture, which can accomplish performance grading with a high confidence and short test application time. Moreover, the proposed architecture can be used for on-line circuit failure prediction and detection. Experimental results are presented to validate the proposed architecture.

[1]  Songwei Pei,et al.  A unified test architecture for on-line and off-line delay fault detections , 2011, 29th VLSI Test Symposium.

[2]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[3]  Baris Taskin,et al.  Delay insertion method in clock skew scheduling , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Dawit Belete,et al.  Use of DFT techniques in speed grading a 1 GHz+ microprocessor , 2002, Proceedings. International Test Conference.

[5]  Mark Mohammad Tehranipoor,et al.  Path-RO: A novel on-chip critical path delay measurement under process variations , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[6]  Ming-Chien Tsai,et al.  An All-Digital High-Precision Built-In Delay Time Measurement Circuit , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[7]  Songwei Pei,et al.  A Low Overhead On-Chip Path Delay Measurement Circuit , 2009, 2009 Asian Test Symposium.

[8]  Edward J. McCluskey,et al.  On-line delay testing of digital circuits , 1994, Proceedings of IEEE VLSI Test Symposium.

[9]  Mehrdad Nourani,et al.  Testing On-Die Process Variation in Nanometer VLSI , 2006, IEEE Design & Test of Computers.

[10]  Sunil P. Khatri,et al.  A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements , 2008, 2008 Design, Automation and Test in Europe.

[11]  Edward J. McCluskey,et al.  DELAY TESTING OF DIGITAL CIRCUITS BY OUTPUT WAVEFORM ANALYSIS , 1991, 1991, Proceedings. International Test Conference.

[12]  Kaushik Roy,et al.  Profit Aware Circuit Design Under Process Variations Considering Speed Binning , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Kaushik Roy,et al.  A novel on-chip delay measurement hardware for efficient speed-binning , 2005, 11th IEEE International On-Line Testing Symposium.

[14]  Xiaowei Li,et al.  A unified online Fault Detection scheme via checking of Stability Violation , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[15]  Jacob A. Abraham,et al.  On-chip delay measurement for silicon debug , 2004, GLSVLSI '04.

[16]  Baris Taskin,et al.  Delay Insertion Method in Clock Skew Scheduling , 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Alfred L. Crouch,et al.  A Production IR-Drop Screen on a Chip , 2007, IEEE Design & Test of Computers.

[18]  Rohit Kapur,et al.  Speed binning with path delay test in 150-nm technology , 2003, IEEE Design & Test of Computers.

[19]  Ming Zhang,et al.  Circuit Failure Prediction and Its Application to Transistor Aging , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[20]  Jacob A. Abraham,et al.  On correlating structural tests with functional tests for speed binning of high performance design , 2004, 2004 International Conferce on Test.

[21]  Cecilia Metra,et al.  Sensing circuit for on-line detection of delay faults , 1996, IEEE Trans. Very Large Scale Integr. Syst..