An efficient design of residue to binary converter for four moduli set (2n-1, 2n+1, 22n-2, 22n+1-3) based on new CRT II

In this paper, an efficient residue to binary converter design for four moduli set (2^n-1,2^n+1,2^2^n-2,2^2^n^+^1-3) is presented. The converter design is based on New Chinese Remainder Theorem 2 (New CRT II). This moduli set has more dynamic range than previous converter designs for four moduli set. The converter is adder-based and memory-less, enabling this design to achieve more speed and less hardware complexity.

[1]  Yuke Wang.  Residue-to-binary converters based on new Chinese remainder theorems , 2000 .

[2]  M.N.S. Swamy,et al.  Residue to binary number converters for three moduli set , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[3]  Graham A. Jullien,et al.  An efficient 3-modulus residue to binary converter , 1996, Proceedings of the 39th Midwest Symposium on Circuits and Systems.

[4]  P.V. Ananda Mohan,et al.  Novel RNS to binary converters , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[5]  F. J. Taylor,et al.  Residue Arithmetic A Tutorial with Examples , 1984, Computer.

[6]  Chip-Hong Chang,et al.  An efficient reverse converter for the 4-moduli set {2/sup n/ - 1, 2/sup n/, 2/sup n/ + 1, 2/sup 2n/ + 1} based on the new Chinese remainder theorem , 2003 .

[7]  Richard I. Tanaka,et al.  Residue arithmetic and its applications to computer technology , 1967 .

[8]  Chip-Hong Chang,et al.  Design of residue-to-binary converter for a new 5-moduli superset residue number system , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[9]  S. Piestrak.  A high-speed realization of a residue to binary number system converter , 1995 .

[10]  Graham A. Jullien,et al.  A VLSI implementation of residue adders , 1987 .

[11]  Chip-Hong Chang,et al.  Design of a high speed reverse converter for a new 4-moduli set residue number system , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[12]  Ahmad A. Hiasat,et al.  An arithmetic residue to binary conversion technique , 2003, Integr..

[13]  Chien-Yuan Chen,et al.  An efficient parity detection technique using the two-moduli set {2h - 1, 2h + 1} , 2006, Inf. Sci..

[14]  Ming-Hwa Sheu,et al.  An efficient VLSI design for a residue to binary converter for general balance moduli (2n-3, 2n+1, 2n-1, 2n+3) , 2004, IEEE Trans. Circuits Syst. II Express Briefs.

[15]  Pepe Siy,et al.  Four-moduli set (2, 2n−1, 2n+2n−1−1, 2n+1+2n−1) simplies the residue to binary converters based on CRT II , 2002 .

[16]  Michael A. Soderstrand,et al.  Residue number system arithmetic: modern applications in digital signal processing , 1986 .

[17]  R. Jacob Baker,et al.  CMOS Circuit Design, Layout, and Simulation , 1997 .

[18]  Thambipillai Srikanthan,et al.  A reverse converter for the 4-moduli superset {2/sup n/-1, 2/sup n/, 2/sup n/+1, 2/sup n+1/+1} , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).

[19]  M.N.S. Swamy,et al.  Residue-to-binary number converters for three moduli sets , 1999 .

[20]  T. Srikanthan,et al.  Fast residue-to-binary converter architectures , 1999, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356).

[21]  Michael J. Flynn,et al.  Introduction to Arithmetic for Digital Systems Designers , 1995 .

[22]  Thanos Stouraitis.  Efficient convertors for residue and quadratic-residue number systems , 1992 .

[23]  A. P. Vinod.  A MEMORYLESS REVERSE CONVERTER FOR THE 4-MODULI SUPERSET {2n - 1, 2n, 2n + 1, 2n + 1 - 1} , 2000 .

[24]  Gian Carlo Cardarilli,et al.  RNS-to-binary conversion for efficient VLSI implementation , 1998 .

[25]  R. Jacob Baker,et al.  CMOS Circuit Design, Layout, and Simulation, Second Edition , 2004 .

[26]  Dimitrios Soudris,et al.  Designing RNS and QRNS full adder based converters , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).