Polyphase filterbanks for symbol timing synchronization in sampled data receivers

Symbol timing synchronization is an important component in a receiver designed to recover data from a digitally modulated waveform. Current trends favor sampled data architectures to perform the synchronization, matched filtering, and detection required to recover the data. Symbol timing synchronizers in a sampled data receiver differ from their continuous-time counterparts: the functionality in a sampled data receiver is an adaptive interpolator as opposed to a sample and hold. This paper describes the use of a polyphase filter bank for symbol timing synchronizers in sampled data receivers. Using this approach, interpolation and matched filtering are rolled into a single operation that requires less resources than separate filters for matched filtering and interpolation. Interpolations are realized by filter bank index selection. Since the filter bank index plays the role of the fractional interpolation interval, the same loop control techniques used in other sampled data synchronizers can be used. Maximum likelihood timing synchronization techniques as well as "early-late gate" techniques can be incorporated into the polyphase filter bank in a natural way.

[1]  William G. Cowley,et al.  The performance of two symbol timing recovery algorithms for PSK demodulators , 1994, IEEE Trans. Commun..

[2]  Norman C. Beaulieu,et al.  Performance of a digital symbol synchronizer in cochannel interference and noise , 2000, IEEE Trans. Commun..

[3]  Marco Luise,et al.  Optimization of symbol timing recovery for QAM data demodulators , 1996, IEEE Trans. Commun..

[4]  Floyd M. Gardner,et al.  Interpolation in digital modems. I. Fundamentals , 1993, IEEE Trans. Commun..

[5]  A. Jennings,et al.  Data-Sequence Selective Timing Recovery for PAM Systems , 1985, IEEE Trans. Commun..

[6]  Lars Erup,et al.  Interpolation in digital modems. II. Implementation and performance , 1993, IEEE Trans. Commun..

[7]  C. W. Farrow,et al.  A continuously variable digital delay element , 1988, 1988., IEEE International Symposium on Circuits and Systems.

[8]  K. Mueller,et al.  Timing Recovery in Digital Synchronous Data Receivers , 1976, IEEE Trans. Commun..

[9]  Heinrich Meyr,et al.  Digital communication receivers - synchronization, channel estimation, and signal processing , 1997, Wiley series in telecommunications and signal processing.

[10]  Michael Rice,et al.  Synchronization in software radios. Carrier and timing recovery using FPGAs , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

[11]  John G. Proakis,et al.  Digital Communications , 1983 .

[12]  Michael Rice,et al.  Multirate digital filters for symbol timing synchronization in software defined radios , 2001, IEEE J. Sel. Areas Commun..

[13]  Floyd M. Gardner,et al.  Phaselock techniques , 1984, IEEE Transactions on Systems, Man, and Cybernetics.

[14]  F. Harris Multirate digital filters used for timing recovery in digital receivers , 2000, Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154).