A harmonic-rejection mixer with improved design algorithm for broadband TV tuners

A wide-band harmonic rejection mixer for TV tuners with an improved design algorithm is fabricated in 65-nm CMOS process. A more realistic mathematical formula is derived to calculate harmonic rejection performance. The third and fifth order harmonic rejection ratio calculation, based on the new proposed equations, precisely predicts simulation results. A systematic design optimization technique pushes the mean of the harmonic rejection performance to a higher value resulting in better yield. The measured third and fifth order harmonic rejection ratio for 2000 samples is better than -56dBc for VHFI and II bands without increasing any circuit complexity or implementation difficulty.

[1]  Eric A. M. Klumperink,et al.  A 400-to-900 MHz receiver with dual-domain harmonic rejection exploiting adaptive interference cancellation , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[2]  Li Lin,et al.  A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[3]  Kwyro Lee,et al.  A CMOS Harmonic Rejection Mixer With Mismatch Calibration Circuitry for Digital TV Tuner Applications , 2008, IEEE Microwave and Wireless Components Letters.

[4]  Peter J. Vancorenland,et al.  A harmonic rejection mixer robust to RF device mismatches , 2011, 2011 IEEE International Solid-State Circuits Conference.