RunFein: a rapid prototyping framework for Feistel and SPN-based block ciphers

Block ciphers are the most prominent symmetric-key cryptography kernels, serving as fundamental building blocks to many other cryptographic functions. This work presents RunFein, a tool for rapid prototyping of a major class of block ciphers, namely product ciphers (including Feistel network and Substitution permutation network-based block ciphers). RunFein accepts the algorithmic configuration of an existing/new block cipher from the user through a GUI to generate a customized software implementation. The user may choose from various micro-architectural templates (unrolled, pipelined, sub-pipelined) to generate an HDL description of the cipher. Various modes of operation and the NIST test suite may also be included. This high-level design approach eliminates the laborious and repetitive development efforts for VLSI realizations of block ciphers. It allows a quick design exploration, consequently enabling fast benchmarking in terms of critical resource estimation of various versions/configurations of a cipher that varies in terms of security, complexity and performance. Using RunFein, we have successfully implemented some well-known product ciphers and benchmarked their performance without significant degradation against their published hand-crafted implementations in literature.

[1]  Kris Gaj,et al.  Can high-level synthesis compete against a hand-written code in the cryptographic domain? A case study , 2014, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14).

[2]  Werner Schindler,et al.  Random Number Generators for Cryptographic Applications , 2009, Cryptographic Engineering.

[3]  Ingrid Verbauwhede,et al.  Energy, performance, area versus security trade-offs for stream ciphers , 2004 .

[4]  Daniel J. Bernstein,et al.  The Salsa20 Family of Stream Ciphers , 2008, The eSTREAM Finalists.

[5]  Ian Miers,et al.  Charm: a framework for rapidly prototyping cryptosystems , 2013, Journal of Cryptographic Engineering.

[6]  Andrey Bogdanov,et al.  PRESENT: An Ultra-Lightweight Block Cipher , 2007, CHES.

[7]  Brian A. Carter,et al.  Advanced Encryption Standard , 2007 .

[8]  Iwata Tetsu,et al.  AURORA: A Cryptographic Hash Algorithm Family , 2009 .

[9]  Roger M. Needham,et al.  TEA, a Tiny Encryption Algorithm , 1994, FSE.

[10]  Sandeep K. Shukla,et al.  Hardware Coprocessor Synthesis from an ANSI C Specification , 2009, IEEE Design & Test of Computers.

[11]  Alfred Menezes,et al.  Handbook of Applied Cryptography , 2018 .

[12]  Elaine B. Barker,et al.  A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications , 2000 .

[13]  Anne Canteaut,et al.  Sosemanuk, a Fast Software-Oriented Stream Cipher , 2008, The eSTREAM Finalists.

[14]  John B. Lacy CryptoLib: Cryptography in Software , 1993, USENIX Security Symposium.

[15]  Vincent Rijmen,et al.  The WHIRLPOOL Hashing Function , 2003 .

[16]  Ivica Nikolic,et al.  Rotational Cryptanalysis of ARX , 2010, FSE.

[17]  Goutam Paul,et al.  CoARX: A coprocessor for ARX-based cryptographic algorithms , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[18]  Christof Paar,et al.  Pushing the Limits: A Very Compact and a Threshold Implementation of AES , 2011, EUROCRYPT.

[19]  Stefan Lucks,et al.  The Skein Hash Function Family , 2009 .

[20]  Sorin A. Huss,et al.  Rapid prototyping for hardware accelerated elliptic curve public-key cryptosystems , 2001, Proceedings 12th International Workshop on Rapid System Prototyping. RSP 2001.

[21]  Guido Bertoni,et al.  Keccak sponge function family main document , 2009 .

[22]  Goutam Paul,et al.  RAPID-FeinSPN: A Rapid Prototyping Framework for Feistel and SPN-Based Block Ciphers , 2013, ICISS.

[23]  Goutam Paul,et al.  Analysis of RC4 and Proposal of Additional Layers for Better Security Margin , 2008, IACR Cryptol. ePrint Arch..

[24]  Hongjun Wu,et al.  The Stream Cipher HC-128 , 2008, The eSTREAM Finalists.

[25]  Christof Paar,et al.  Ultra-Lightweight Implementations for Smart Devices - Security for 1000 Gate Equivalents , 2008, CARDIS.

[26]  Albert Koelmans,et al.  Dynamic global security-aware synthesis using SystemC , 2007, IET Comput. Digit. Tech..

[27]  Kris Gaj,et al.  Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study , 2015, ARC.

[28]  A. Chattopadhyay,et al.  Exploring security-performance trade-offs during hardware accelerator design of stream cipher RC4 , 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

[29]  Rainer Leupers,et al.  LISA: A Uniform ADL for Embedded Processor Modeling, Implementation, and Software Toolsuite Generation , 2008 .

[30]  Samuel Williams,et al.  The Landscape of Parallel Computing Research: A View from Berkeley , 2006 .

[31]  Akashi Satoh,et al.  A Compact Rijndael Hardware Architecture with S-Box Optimization , 2001, ASIACRYPT.

[32]  W. Marsden I and J , 2012 .

[33]  Kris Gaj,et al.  ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[34]  Morris J. Dworkin,et al.  Recommendation for Block Cipher Modes of Operation: Methods and Techniques , 2001 .

[35]  Ronald L. Rivest,et al.  The MD5 Message-Digest Algorithm , 1992, RFC.

[36]  Morris J. Dworkin,et al.  Recommendation for Block Cipher Modes of Operation: Methods for Key Wrapping , 2012 .