Analysis of Low Power High Performance XOR Gate Using GDI Technique
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[1] Anantha P. Chandrakasan,et al. Low-power CMOS digital design , 1992 .
[2] Anantha P. Chandrakasan,et al. Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.
[3] Gary K. Yeap,et al. INTRODUCTION TO LOW-POWER VLSI DESIGN , 1996 .
[4] Rajeevan Chandel,et al. Design and Analysis of a Modified Low Power CMOS Full Adder Using Gate-Diffusion Input Technique , 2010, J. Low Power Electron..
[5] Tarek Darwish,et al. Performance analysis of low-power 1-bit CMOS full adder cells , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[6] Jan M. Rabaey,et al. Digital Integrated Circuits , 2003 .
[7] Wolfgang Fichtner,et al. Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.
[8] Taikyeong T. Jeong. Implementation of low power adder design and analysis based on power reduction technique , 2008, Microelectron. J..
[9] Kuo-Hsing Cheng,et al. The novel efficient design of XOR/XNOR function for adder applications , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).
[10] Alexander Fish,et al. Gate-diffusion input (GDI)-a novel power efficient method for digital circuits: a design methodology , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).
[11] Israel A. Wagner,et al. Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[12] Gary K. Yeap,et al. Practical Low Power Digital VLSI Design , 1997 .
[13] Shin Min Kang,et al. CMOS Digital Integrated Cir-cuits: Analysis and Design , 2002 .
[14] John P. Uyemura,et al. Circuit design for CMOS VLSI , 1992 .