A processor for testing mixed-signal cores in system-on-chip

This paper describes the design of a processor specific for testing cores embedded in system-on-chip. This processor, which can be implemented within a system's reconfigurable area, shall be responsible for scheduling and control test operations and perform preliminary data processing, as well as to provide the interface with an external tester. Building these test operations on-chip allows for simplifying external tester interface and to reduce testing time. The testing procedure and the infrastructure required to test an A/D converter is described as an example.

[1]  Rochit Rajsuman.  Testing a system-on-a-chip with embedded microprocessor , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[2]  José Silva Matos,et al.  A boundary scan test controller for hierarchical BIST , 1992, Proceedings International Test Conference 1992.

[3]  Heinrich Theodor Vierhaus,et al.  A test processor concept for systems-on-a-chip , 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[4]  Giovanni Squillero,et al.  On the test of microprocessor IP cores , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[5]  M.A. AbdEl-Halim.  An analog mixed-signal test controller , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[6]  Jose Machado da Silva,et al.  Functional in-circuit characterisation of ΣΔ modulators , 2002 .

[7]  Nur A. Touba,et al.  Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor , 2002, J. Electron. Test..