A mixed analog/digital asynchronous processor for cortical computations in 3D SOI-CMOS

We present a system level architecture for a scalable, mixed-signal, asynchronous processor, aimed at cortical computations. The design has been implemented in MIT Lincoln Lab's three-tier SOI-CMOS 0.18mum digital process. The main circuits are distributed in the two tiers; an asynchronous address-event based read/write middle tier and an odd symmetric spatial filter (8 orientations) on the bottom tier. The top tier includes a photosensitive pixel array (64times64) to facilitate testing and characterization of the system. A highspeed 2-phase asynchronous chip-to-chip communication protocol is built-in to facilitate system scalability

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