System-Level Modeling of a NoC-Based H.264 Decoder

Networks-on-chip (NoC) are expected to play a key role in future embedded systems. A NoC-based system has the potential to support concurrent processing, in both software and hardware. This can however lead to concurrency issues. We present a multiprocessor system modeling and performance evaluation approach that addresses concurrency. We illustrate our methodology by mapping a H.264 decoder onto a 4 x 3 mesh- based NoC architecture. We show latency, area, and power consumption results for this NoC architecture abstracted from its FPGA implementation.

[1]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[2]  Vu-Duc Ngo,et al.  The Optimized Tree-based Network on Chip Topologies for H.264 Decoder Design , 2006, 2006 International Conference on Computer Engineering and Systems.

[3]  Peter H. N. de With,et al.  Qos concept for scalable MPEG-4 video object decoding on multimedia (NoC) chips , 2006, IEEE Transactions on Consumer Electronics.

[4]  D. Marpe,et al.  The H . 264 / AVC Video Coding Standard , 2004 .

[5]  E. Filippi,et al.  An outlook on the evolution of mobile terminals: from monolithic to modular multiradio, multiapplication platforms , 2006, IEEE Circuits and Systems Magazine.

[6]  Axel Jantsch,et al.  Networks on chip , 2003 .

[7]  Jörg Henkel,et al.  H. 264 HDTV Decoder Using Application-Specific Networks-On-Chip , 2005, 2005 IEEE International Conference on Multimedia and Expo.

[8]  William F. Gilreath,et al.  Concurrency State Models and Java Programs , 2000, Parallel Distributed Comput. Pract..

[9]  Hari Kalva,et al.  Resource estimation methodology for multimedia applications , 2007, Electronic Imaging.

[10]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[11]  G. M. Callico,et al.  Towards a configurable SoC MPEG-4 advanced simple profile decoder , 2007, IET Comput. Digit. Tech..

[12]  H. Kalva.  The H.264 Video Coding Standard , 2006, IEEE MultiMedia.

[13]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[14]  A. Agarwal,et al.  Concurrency Compliant Embedded System Modeling Methodology , 2008, 2008 2nd Annual IEEE Systems Conference.

[15]  Partha Pratim Pande,et al.  Performance evaluation and design trade-offs for network-on-chip interconnect architectures , 2005, IEEE Transactions on Computers.

[16]  Vu-Duc Ngo,et al.  Realizing Network on Chip Design of H.264 Decoder Based on Throughput Aware Mapping , 2006, 2006 First International Conference on Communications and Electronics.