Fine-grain abstraction and sequential do not cares for large scale model checking

Abstraction refinement is a key technique for applying model checking to the verification of real-world digital systems. In previous work, the abstraction granularity is often limited at the state variable level, which is too coarse for verifying industrial-scale designs. In this paper, we propose a finer grain abstraction in which intermediate variables are selectively inserted to partition large combinational logic cones into smaller pieces; these intermediate variables, together with the state variables, are then treated as "atoms" in abstraction refinement. With this fine-grain approach, refinement is conducted in two different directions, sequential and Boolean. We propose a SAT-based method for predicting the appropriate refinement direction, and apply greedy minimization in both directions to keep the refinement set small. We also explore the use of approximate reachable states of the remaining submodules to help verifying the abstract model. Experimental studies show that the proposed techniques significantly improve the performance of abstraction refinement, and therefore increase the model checker's ability to handle large designs.

[1]  Zijiang Yang,et al.  Iterative Abstraction using SAT-based BMC with Proof Analysis , 2003, ICCAD 2003.

[2]  Enrico Macii,et al.  Algorithms for approximate FSM traversal based on state space decomposition , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Ofer Strichman,et al.  SAT Based Abstraction-Refinement Using ILP and Machine Learning Techniques , 2002, CAV.

[4]  Bing Li,et al.  Improving Ariadne's Bundle by following multiple threads in abstraction refinement , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[5]  Helmut Veith,et al.  Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis , 2002, FMCAD.

[6]  Moshe Y. Vardi,et al.  Multiple-Counterexample Guided Iterative Abstraction Refinement: An Industrial Evaluation , 2003, TACAS.

[7]  Jiang Long,et al.  Formal property verification by abstraction refinement with formal, simulation and hybrid engines , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[8]  Olivier Coudert,et al.  A unified framework for the formal verification of sequential circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[9]  Edmund M. Clarke,et al.  Counterexample-guided abstraction refinement , 2003, 10th International Symposium on Temporal Representation and Reasoning, 2003 and Fourth International Conference on Temporal Logic. Proceedings..

[10]  Chao Wang,et al.  A satisfiability-based approach to abstraction refinement in model checking , 2003, BMC@CAV.

[11]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[12]  Tiziano Villa,et al.  VIS: A System for Verification and Synthesis , 1996, CAV.

[13]  Kenneth L. McMillan,et al.  Automatic Abstraction without Counterexamples , 2003, TACAS.