Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability

This paper presents an exact method which finds the minimum factored form of an incompletely specified Boolean function. The problem is formulated as a Quantified Boolean Formula (QBF) and is solved by general-purpose QBF solver. We also propose a novel graph structure, called an X-B (eXchanger Binary) tree, which compactly and implicitly enumerates binary trees. Leveraged by this graph structure, the factoring problem is transformed into a QBF. Using three sets of benchmark functions: artificially-created, randomly-generated and ISCAS 85 benchmark functions, we empirically demonstrate the quality of the solutions and the runtime complexity of the proposed method.

[1]  Marco Benedetti,et al.  a QBF decision procedure based on Propositional Skolemization and Symbolic Reasoning , 2004 .

[2]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[3]  Shmuel Zaks,et al.  Lexicographic Generation of Ordered Trees , 1980, Theor. Comput. Sci..

[4]  R. Drechsler,et al.  Exact Circuit Synthesis , 1998 .

[5]  Reinhold Letz,et al.  Lemma and Model Caching in Decision Procedures for Quantified Boolean Formulas , 2002, TABLEAUX.

[6]  Tracy Larrabee,et al.  Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Joao Marques-Silva,et al.  GRASP-A new search algorithm for satisfiability , 1996, Proceedings of International Conference on Computer Aided Design.

[8]  Armin Biere,et al.  Resolve and Expand , 2004, SAT.

[9]  Andrzej Proskurowski.  On the Generation of Binary Trees , 1980, JACM.

[10]  Edward S. Davidson,et al.  An Algorithm for NAND Decomposition Under Network Constraints , 1969, IEEE Transactions on Computers.

[11]  Burkhard Monien,et al.  A Distributed Algorithm to Evaluate Quantified Boolean Formulae , 2000, AAAI/IAAI.

[12]  Jason Cong,et al.  RASP: A General Logic Synthesis System for SRAM-Based FPGAs , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.

[13]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[14]  Armin Biere,et al.  Symbolic Model Checking without BDDs , 1999, TACAS.

[15]  Eugene L. Lawler,et al.  An Approach to Multilevel Boolean Minimization , 1964, JACM.

[16]  Makoto Ikeda,et al.  Exact Minimum Logic Factoring via Quantified Boolean Satisfiability , 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

[17]  Jōhō Shori Gakkai,et al.  IPSJ Transactions on system LSI design methodology , 2008 .

[18]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Daniel Brand.  Verification of large synthesized designs , 1993, ICCAD.