On-Line Testing and Reconfiguration of Field Programmable Gate Arrays (FPGAs) for Fault-Tolerant (FT) Applications in Adaptive Computing Systems (ACS)
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[1] Patrick Juola,et al. An approach for the yield enhancement of programmable gate arrays , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[2] Charles E. Stroud,et al. Enhanced BIST-based diagnosis of FPGAs via boundary scan access , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).
[3] Kaushik Roy,et al. On Routability for FPGAs under Faulty Conditions , 1995, IEEE Trans. Computers.
[4] Yasuo Kawahara,et al. Introducing redundancy in field programmable gate arrays , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.
[5] Shantanu Dutt,et al. REMOD: a new methodology for designing fault-tolerant arithmetic circuits , 1997, IEEE Trans. Very Large Scale Integr. Syst..
[6] J. Narasimhan,et al. Yield enhancement of wafer scale integrated arrays , 1991, 1991 Proceedings, International Conference on Wafer Scale Integration.
[7] Parag K. Lala,et al. On-line testable logic design for FPGA implementation , 1997, Proceedings International Test Conference 1997.
[8] Andreas Steininger,et al. On the necessity of on-line-BIST in safety-critical applications-a case-study , 1999, Digest of Papers. Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing (Cat. No.99CB36352).
[9] Edward J. McCluskey,et al. Finite state machine synthesis with concurrent error detection , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[10] Fabrizio Lombardi,et al. An approach for testing programmable/configurable field programmable gate arrays , 1996, Proceedings of 14th VLSI Test Symposium.
[11] Shantanu Dutt,et al. Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).
[12] Jonathan Rose,et al. Partial Reconfiguration of FPGA Mapped Designs with Applications to Fault Tolerance and Yield Enhancement , 1997 .
[13] Peter A. Ivey,et al. Defect tolerant SRAM based FPGAs , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[14] Charles E. Stroud,et al. Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[15] Miodrag Potkonjak,et al. Low overhead fault-tolerant FPGA systems , 1998, IEEE Trans. Very Large Scale Integr. Syst..
[16] Charles E. Stroud,et al. (Finally, A Free Lunch: BIST Without Overhead!) , 1996 .
[17] Charles E. Stroud,et al. Built-in self-test of FPGA interconnect , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[18] Andrew M. Tyrrell,et al. The yield enhancement of field-programmable gate arrays , 1994, IEEE Trans. Very Large Scale Integr. Syst..
[19] Miodrag Potkonjak,et al. Algorithms for efficient runtime fault recovery on diverse FPGA architectures , 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).
[20] Dinesh K. Bhatia,et al. A Fault Tolerant Technique for FPGAs , 2000, J. Electron. Test..
[21] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[22] Shantanu Dutt,et al. Efficient network-flow based techniques for dynamic fault reconfiguration in FPGAs , 1999, Digest of Papers. Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing (Cat. No.99CB36352).
[23] Ping Chen,et al. Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.
[24] Charles E. Stroud,et al. BIST-based test and diagnosis of FPGA logic blocks , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[25] M. Sipper,et al. Toward robust integrated circuits: The embryonics approach , 2000, Proceedings of the IEEE.
[26] Russell Tessier,et al. Diagnosis of interconnect faults in cluster-based FPGA architectures , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[27] Hideo Fujiwara,et al. Universal Fault Diagnosis for Lookup Table FPGAs , 1998, IEEE Des. Test Comput..
[28] Y. Zorian,et al. SRAM-based FPGA's: testing the LUT/RAM modules , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[29] Shantanu Dutt,et al. Methodologies for Tolerating Cell and Interconnect Faults in FPGAs , 1998, IEEE Trans. Computers.
[30] A. J. van de Goor,et al. Testing Semiconductor Memories: Theory and Practice , 1998 .
[31] Charles E. Stroud,et al. On-line BIST and diagnosis of FPGA interconnect using roving STARs , 2001, Proceedings Seventh International On-Line Testing Workshop.
[32] Moshe Sipper,et al. Toward self-repairing and self-replicating hardware: the Embryonics approach , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.
[33] Charles E. Stroud,et al. Dynamic fault tolerance in FPGAs via partial reconfiguration , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).
[34] Russell Tessier,et al. Interconnect testing in cluster-based FPGA architectures , 2000, Proceedings 37th Design Automation Conference.
[35] Sying-Jyan Wang,et al. Test and diagnosis of faulty logic blocks in FPGAs , 1999 .
[36] Edward J. McCluskey. Verification Testing - A Pseudoexhaustive Test Technique , 1984, IEEE Trans. Computers.
[37] Yervant Zorian,et al. Testing the Interconnect of RAM-Based FPGAs , 1998, IEEE Des. Test Comput..
[38] John M. Emmert,et al. Incremental routing in FPGAs , 1998, Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372).
[39] Yervant Zorian,et al. SRAM-Based FPGAs: Testing the Embedded RAM Modules , 1999, J. Electron. Test..
[40] George Varghese,et al. HSRA: high-speed, hierarchical synchronous reconfigurable array , 1999, FPGA '99.
[41] Charles E. Stroud,et al. BIST-based diagnostics of FPGA logic blocks , 1997, Proceedings International Test Conference 1997.
[42] N. Hastie,et al. The implementation of hardware subroutines on field programmable gate arrays , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.
[43] Charles E. Stroud,et al. Performance Penalty for Fault Tolerance in Roving STARs , 2000, FPL.
[44] Kazuo Nakajima,et al. Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[45] M. Abramovici,et al. Improving on-line BIST-based diagnosis for roving STARs , 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).
[46] Russell Tessier,et al. Tolerating operational faults in cluster-based FPGAs , 2000, FPGA '00.
[47] Fabrizio Lombardi,et al. Diagnosing Programmable Interconnect Systems for FPGAs , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.
[48] Hideo Fujiwara,et al. A test methodology for interconnect structures of LUT-based FPGAs , 1996, Proceedings of the Fifth Asian Test Symposium (ATS'96).
[49] Fabrizio Lombardi,et al. Testing configurable LUT-based FPGA's , 1998, IEEE Trans. Very Large Scale Integr. Syst..
[50] Miodrag Potkonjak,et al. On-line fault detection for bus-based field programmable gate arrays , 1998, IEEE Trans. Very Large Scale Integr. Syst..