High performance CMOS for GHz communication IC

A 0.35 /spl mu/m design rule except for gate length was applied to CMOS ICs for giga hertz, low-power operation. To obtain such high speed switching, the gate was reduced to 0.15 /spl mu/m and parasitic capacitance was greatly reduced by a localized channel implant. Using this design technique, a 1:8 DEMUX for optical communication was developed, and has achieved high speed, low-power operation of 2.8 GHz/220 mW (@V/sub DD/=2 V) and 2.6 GHz/37 mW (@V/sub DD/=1 V). This technique was shown to be most effective in fields that require speeds greater than about 1 GHz but do not necessarily require large scale integration.