DesignCon 2006 A Co-design Methodology of Signal Integrity and Power Integrity

As PCB interconnection density and channel data rate are getting increasingly higher, various 3D effects, crosstalk, and discontinuity-induced ISI are playing a much more important role, for both signal channels and power distribution networks. In particular, noise coupling between signal trace and power delivery network has become a key issue and performance limiter for high-speed chip-to-chip interface, which must be addressed appropriately. Understanding these combined signal integrity (SI) and power integrity (PI) issues in the era of gigahertz data rates requires advanced co-design methodology for SI and PI analysis. In this paper, a robust co-design methodology is established and successfully demonstrated through two case studies: investigations of DDR2-800 control bus resonance problem and DDR2-667 Vref bus noise issue. With traditional signal integrity simulations which consider an ideal power delivery system; these issues may not be observable until the post-silicon validation stage. With the co-design methodology, however, as root-causes of these issues are identified, more cost-effective resolutions become apparent at the pre-silicon design stage. Design guidelines, which were summarized from the two case studies regarding noise coupling by 3D effect and resonant structure, are demonstrated as follows: first, plane noise specification requires less than 150mV at the transition layer; second, to reduce plane-signal coupling, it's recommended that no reference layer change occur unless absolutely required; third, the stitch distance has to be much shorter than wavelength of the third harmonic of maximum digital frequency, and; fourth, resonance needs to be alleviated by keeping out critical lengths such as half and quarter wavelength at frequencies of interest. where he is currently a Staff Analog Engineer. He has been working on GHz system Signal Integrity (SI) analysis, high-speed VLSI interconnect, microwave package modeling, RF circuit design, and over GHz and low-power clock distribution. He has authored and co-authored more than 50 technical publications including 2 issued and 3 pending patents, journals, and conference proceeding papers. He is an IEEE member and a reviewer for IEEE MTT/AP and DAC. Currently at Intel, he is focused on researching and developing next generation memory technology, multi-giga-hertz bus interfaces, and signal integrity, power integrity, and jitter analysis methodologies. He is a member of Sigma Xi, IEEE, and reviewer for several IEEE journals and international conferences.