NoC Dynamically Reconfigurable as TAM

When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUTs). To facilitate the network on chip (NoC) testing, test engineers frequently focus on reusing the NoC as TAM, in which, communication infrastructure of the NoC (routers, interconnection links, protocolsc) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data are exchanged in packets. Based on this drawback, this paper presents a new method which consists of reconfiguring the NoC hardware dynamically to act as a TAM. This configurability allows us to have the granularity of the traditional TAM which facilitates test scheduling, and the advantages of the NoC communication infrastructure, which give us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM method and a TAM architecture named T2-TAM using two ITC'02 benchmark circuits. The presented results show a test time reduction between 6% and 55% while imposing less than 9.6% area overhead.

[1]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[2]  Petru Eles,et al.  Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns , 2008, 2008 Design, Automation and Test in Europe.

[3]  Dhiraj K. Pradhan,et al.  Test scheduling for network-on-chip with BIST and precedence constraints , 2004, 2004 International Conferce on Test.

[4]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[5]  Hideo Fujiwara,et al.  An SoC Test Scheduling Algorithm using Reconfigurable Union Wrappers , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[6]  Huawei Li,et al.  T2- TAM:Reusing infrastructure resource to provide parallel testing for NoC based Chip , 2009, 2009 IEEE 8th International Conference on ASIC.

[7]  Alexandre M. Amory,et al.  Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism , 2007, IET Comput. Digit. Tech..

[8]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[9]  Sungju Park,et al.  Parallel test method for NoC-based SoCs , 2009, 2009 International SoC Design Conference (ISOCC).

[10]  Erik Jan Marinissen,et al.  Effective and efficient test architecture design for SOCs , 2002, Proceedings. International Test Conference.

[11]  Partha Pratim Pande,et al.  Design of a switch for network on chip applications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[12]  Erik Jan Marinissen,et al.  A set of benchmarks for modular testing of SOCs , 2002, Proceedings. International Test Conference.

[13]  Erik Jan Marinissen,et al.  On using rectangle packing for SOC wrapper/TAM co-optimization , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[14]  Luigi Carro,et al.  Power-aware noc reuse on the testing of core-based systems , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[15]  Alexandre M. Amory,et al.  A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms , 2011, J. Parallel Distributed Comput..