SELF CHECKING AND FAULT TOLERANT DIGITAL DESIGN

During the process of development of any system, system reliability is of utmost importance. Specially when designing a processor, it is desired that a processor function correctly even in the presence of faults. This concept is commonly referred to as fault tolerance. The fault tolerant microprocessor systems used in safety critical applications need to be thoroughly validated during the design stages. As feature size reduces in future, there is an increased probability of transient and inter mittent faults. Now these systems on chip integrated circuits contain both digital and analog cores. Test cost for such mixed signal SOC is much higher than the digital SOC that allows the analog and digital cores to be tested. The analog cores are wrapped such that the test can performed using a digital test access mechanism. In our method, an analog test infrastructure is used which consists of test wrapper s and test access mechanism. Test wrappers isolate var ious modules from their surrounding circuitry during test. So the focus is on optimisation of a unified test access architecture that is used for digital and analo gue cores. We wrap each analog core by a pair of digital to analog converter and analog to digital converter. They convert analog core to virtual digital core which allow the use of digital testers to test the analog cores. This reduces the need for expensi ve mixed signal tester so that there is a reduction in the overall cost.

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