Power-effective ROM-less DDFS Design Approach with High SFDR Performance

A ROM-less direct digital frequency synthesizer (DDFS) design approach based on interpolation schemes is proposed in this work. Besides achieving higher SFDR (spurious free dynamic range) and faster clock rate, detailed power estimation approach based on switching activity analysis of each logic sub-blocks is presented to explore the optimal solution. The parabolic equations with proper selection of coefficients and pipeline structure are utilized to enhance SFDR. A ROM-less DDFS using the proposed design approach is demonstrated by the physical implementation on Altera FPGA platform. The average SFDR is measured to be 68.4242 dBc with 1.1659 dBc deviation over 33 times of experiments. The measured SFDR is proved to outperform many previous DDFS works even if they were implemented on silicon.

[1]  Haifeng Sun,et al.  Low-Noise Microwave Performance of 0.1 $\mu$m Gate AlInN/GaN HEMTs on SiC , 2010, IEEE Microwave and Wireless Components Letters.

[2]  Ioannis Pitas,et al.  Guest Editorial: Special Issue on Machine Learning for Signal Processing , 2010, J. Signal Process. Syst..

[3]  B. Gold,et al.  A digital frequency synthesizer , 1971 .

[4]  Y. Savaria,et al.  Precise free-running period synthesizer (FRPS) with process and temperature compensation , 2007, 2007 50th Midwest Symposium on Circuits and Systems.

[5]  Zhihua Wang,et al.  A Fast Settling Dual-Path Fractional- $N$ PLL With Hybrid-Mode Dynamic Bandwidth Control , 2010, IEEE Microwave and Wireless Components Letters.

[6]  Chua-Chin Wang,et al.  A ROM-less DDFS Based on a Parabolic Polynomial Interpolation Method with an Offset , 2011, J. Signal Process. Syst..

[7]  Paulo Roberto de Carvalho,et al.  Area optimized CORDIC-based numerically controlled oscillator for electrical bio-impedance spectroscopy , 2016 .

[8]  Bharadwaj Amrutur,et al.  A comparative study of direct digital frequency synthesizer architectures in 180nm CMOS , 2017, 2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS).

[9]  Paul P. Sotiriadis Timing and spectral properties of the Flying-Adder frequency synthesizers , 2009, 2009 IEEE International Frequency Control Symposium Joint with the 22nd European Frequency and Time forum.

[10]  Feng Zhao,et al.  A 650 MHz DDFS for stretch processing radar in 130nm BiCMOS process , 2013, 2013 European Microwave Integrated Circuit Conference.

[11]  Mohsen Padash,et al.  A 9-bit, 1-giga samples per second sine and cosine direct digital frequency synthesizer , 2014, 2014 22nd Iranian Conference on Electrical Engineering (ICEE).

[12]  Arthur H. M. van Roermund,et al.  Minimum Power-Consumption Estimation in ROM-Based DDFS for Frequency-Hopping Ultralow-Power Transmitters , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Foster F. Dai,et al.  An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC , 2010, IEEE Journal of Solid-State Circuits.

[14]  Wei Wang,et al.  Dynamic power estimation for ROM-less DDFS designs using switching activity analysis , 2017, 2017 International SoC Design Conference (ISOCC).

[15]  Akira Matsuzawa,et al.  A 2 GS/s 118 mW digital-mapping direct digital frequency synthesizer in 65nm CMOS , 2017, 2017 12th European Microwave Integrated Circuits Conference (EuMIC).

[16]  Chia-Hao Hsu,et al.  ROM-less DDFS using non-equal division parabolic polynomial interpolation method , 2011, 2011 International Symposium on Integrated Circuits.

[17]  Chua-Chin Wang,et al.  Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.