Design of the front-end driver card for CMS silicon microstrip tracker readout
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The CMS silicon microstrip tracker has approximately 10 million readout channels. The tracking readout system employs several hundred off-detector Front-End Driver (FED) cards to digitise, sparsify and buffer analogue data arriving via optical links from on-detector pipeline chips (APVs). This paper describes the baseline design of the FrontEnd Driver card which is implemented with a 96 ADC channel (10 bits) 9U VME board. Under typical LHC operating conditions the total input data rate per FED after digitisation is 3 GBytes/s and must be substantially reduced. The required digital data processing is highly parallel and heavily pipelined and is carried out in several large FPGAs. The employment of modern FPGA simulation tools in the design of a VHDL model of the FED is discussed.
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