A New Distributed Test Control Architecture with Multihop Wireless Test Connectivity and Communication for GigaHertz System-Chips ( Extended Summary ) �

With the increase in chip size and complexity, the direct or bus interconnects in conventional SoC test control models are rather restricted. In this paper, we propose a new distributed multihop wireless test control network based on the recent development in “radio-on-chip” technology. The proposed architecture consists of three basic components, the test scheduler, the resource configurators, and the RF nodes which support the communication between the test scheduler and clusters of cores. Under the multilevel tree structure, the resources (including not only the circuit blocks to perform testing, but also the on-chip radio-frequency nodes for intra-chip communication) are properly distributed and system optimization is performed in terms of both test application time and test control cost. Topic Category: System-on-Chip (SOC) Test, System Testing, Test Resource Partitioning

[1]  Kewal K. Saluja,et al.  Test Scheduling and Control for VLSI Built-In Self-Test , 1988, IEEE Trans. Computers.

[2]  Wolfgang Maass,et al.  Approximation schemes for covering and packing problems in image processing and VLSI , 1985, JACM.

[3]  Luigi Carro,et al.  Communication architectures for system-on-chip , 2001, Symposium on Integrated Circuits and Systems Design.

[4]  Alain Greiner,et al.  A Scalable Architecture for System-on-Chip Interconnections , 1999 .

[5]  Zebo Peng,et al.  Test scheduling and scan-chain division under power constraint , 2001, Proceedings 10th Asian Test Symposium.

[6]  Yervant Zorian,et al.  A distributed BIST control scheme for complex VLSI devices , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[7]  Shambhu J. Upadhyaya,et al.  Adaptive test scheduling in SoC's by dynamic partitioning , 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

[8]  Krishnendu Chakrabarty,et al.  Test scheduling for core-based systems using mixed-integer linearprogramming , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Kuen-Jong Lee,et al.  A hierarchical test control architecture for core based design , 2000, Proceedings of the Ninth Asian Test Symposium.

[10]  Christos A. Papachristou,et al.  An ILP formulation to optimize test access mechanism in system-on-chip testing , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[11]  Nilanjan Mukherjee,et al.  Resource allocation and test scheduling for concurrent test of core-based SOC design , 2001, Proceedings 10th Asian Test Symposium.

[12]  Erik Jan Marinissen,et al.  On using rectangle packing for SOC wrapper/TAM co-optimization , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[13]  Krishnendu Chakrabarty.  Design of system-on-a-chip test access architectures using integer linear programming , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[14]  Shambhu J. Upadhyaya,et al.  Power constrained test scheduling with dynamically varied TAM , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[15]  Erik Jan Marinissen,et al.  Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[16]  Vasek Chvátal,et al.  A Greedy Heuristic for the Set-Covering Problem , 1979, Math. Oper. Res..

[17]  Drew Wingard.  MicroNetwork-based integration for SOCs , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[18]  Vwani P. Roychowdhury,et al.  RF/wireless interconnect for inter- and intra-chip communications , 2001, Proc. IEEE.

[19]  Chih-Ming Hung,et al.  Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters , 2002, IEEE J. Solid State Circuits.

[20]  Ronald L. Rivest,et al.  Introduction to Algorithms, Second Edition , 2001 .

[21]  Chi-Yi Hwang,et al.  A hierarchical test scheme for system-on-chip designs , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.