Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technology
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[1] Hai Zhou,et al. Impact of Modern Process Technologies on the Electrical Parameters of Interconnects , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).
[2] Atsushi Kurokawa,et al. Dummy filling methods for reducing interconnect capacitance and number of fills , 2005, Sixth international symposium on quality electronic design (isqed'05).
[3] Chi-Yuan Lo,et al. Parasitic extraction: current state of the art and future trends , 2001 .
[4] D. Ryuzaki,et al. Enhanced dielectric-constant reliability of low-k porous organosilicate glass (k = 2.3) for 45-nm-generation Cu interconnects , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
[5] Xiaopeng Xu,et al. Modeling Process Impact on Cu/Low k Interconnect Performance and Reliability , 2006, 2006 16th Biennial University/Government/Industry Microelectronics Symposium.
[6] Martin D. F. Wong,et al. Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability , 2000, Proceedings 37th Design Automation Conference.
[7] Poras T. Balsara,et al. Benchmarks for interconnect parasitic resistance and capacitance , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..
[8] Andrew B. Kahng,et al. Study of floating fill impact on interconnect capacitance , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).